GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/volteer/var/voxel: Update DPTF parameters 

remove TCC offset setting in overridetree.cb,
use default setting(# TCC of 90) in baseboard.

BUG=b:174547185
BRANCH=volteer
TEST=emerge-volteer coreboot

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Iaac1fae12ccaa8a623bc2dc3105262918523d440
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48264
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sheng-Liang Pan 2020-12-03 18:47:04 +08:00 committed by Tim Wawrzynczak
parent e9eecc902f
commit 9cce83c58e
1 changed files with 0 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/volteer/variants/voxel/overridetree.cb
View File

@ -1,7 +1,6 @@
chip soc/intel/tigerlake
register "DdiPort1Hpd" = "0"
register "DdiPort2Hpd" = "0"
register "tcc_offset" = "5" # TCC of 95
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
.tdp_pl1_override = 18,