soc/intel/apollolake: Get rid of cnvi.asl

There is no need to add a special cnvi.asl file for the CNVi
device. This can be handled by drivers/intel/wifi just like a PCIe
WiFi device. This change gets rid of the cnvi.asl file and its usage
in southbridge.asl file.

BUG=b:112371978

Change-Id: I0b798cdd430768730b7ada61ca4cb1f63c2a4229
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2018-08-09 10:08:34 -07:00
parent c3cbbe6a78
commit 9cd65cd4b5
2 changed files with 0 additions and 36 deletions

View File

@ -1,30 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* CNVi Controller 0:C.0 */
Device (CNVI) {
Name(_ADR, 0x000C0000)
Name (_S3D, 3) /* D3 supported in S3 */
Name (_S0W, 3) /* D3 can wake device in S0 */
Name (_S3W, 3) /* D3 can wake system from S3 */
Name (_PRW, Package() { GPE0A_CNVI_PME_STS, 3 })
Method (_STA, 0)
{
Return (0xF)
}
}

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@ -47,10 +47,4 @@
/* SGX */
#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)
#include <soc/intel/common/acpi/sgx.asl>
/* CNVi */
#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
#include "cnvi.asl"
#endif
#endif