sandybridge/raminit_common: use macro for execute command queue register
This patch doesn't change the hash of a timeless build. Change-Id: I5d329f65be0eee741fd330c0926881ff4f956624 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Felix Held
parent
f9b826ac37
commit
9cf1dd280f
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@ -62,9 +62,11 @@
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* DEFAULT_MCHBAR + 0x4284 + 0x400 * channel: execute command queue
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* Starts to execute all queued commands
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* Bit 0 : start DRAM command execution
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* Bit 16-20: (number of queued commands - 1) * 4
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* Bit 18-19 : number of queued commands - 1
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*/
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#define RUN_QUEUE_4284(x) ((((x) - 1) << 18) | 1) // 0 <= x < 4
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static void sfence(void)
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{
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asm volatile ("sfence");
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@ -643,12 +645,12 @@ static void write_reset(ramctr_timing * ctrl)
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/* DRAM command ZQCS */
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MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003;
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MCHBAR32(0x4230 + 0x400 * channel) = 0x80c01;
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MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000;
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MCHBAR32(0x4210 + 0x400 * channel) = 0;
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MCHBAR32(0x4284 + 0x400 * channel) = 0x400001;
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// execute command queue - why is bit 22 set here?!
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MCHBAR32(0x4284 + 0x400 * channel) = (1 << 22) | RUN_QUEUE_4284(1);
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wait_428c(channel);
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}
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@ -754,7 +756,9 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank,
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MCHBAR32(0x4208 + 0x400 * channel) =
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(slotrank << 24) | (reg << 20) | val | 0x60000;
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MCHBAR32(0x4218 + 0x400 * channel) = 0;
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MCHBAR32(0x4284 + 0x400 * channel) = 0x80001;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(3);
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}
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static u32 make_mr0(ramctr_timing * ctrl, u8 rank)
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@ -889,7 +893,7 @@ void dram_mrscommands(ramctr_timing * ctrl)
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MCHBAR32(0x4e04) = 0x60400;
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MCHBAR32(0x4e14) = 0x288;
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/* execute command queue on all channels ? */
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// execute command queue on all channels? Why isn't bit 0 set here?
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MCHBAR32(0x4e84) = 0x40004;
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// Drain
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@ -920,7 +924,9 @@ void dram_mrscommands(ramctr_timing * ctrl)
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MCHBAR32(0x4200 + 0x400 * channel) =
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(slotrank << 24) | 0x60000;
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MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0;
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MCHBAR32(0x4284 + 0x400 * channel) = 0x1;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1);
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// Drain
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wait_428c(channel);
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@ -1109,7 +1115,8 @@ static void test_timA(ramctr_timing * ctrl, int channel, int slotrank)
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MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x360000;
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MCHBAR32(0x421c + 0x400 * channel) = 0;
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MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4);
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wait_428c(channel);
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}
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@ -1368,7 +1375,9 @@ int read_training(ramctr_timing * ctrl)
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MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16);
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MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400;
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MCHBAR32(0x4210 + 0x400 * channel) = 0;
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MCHBAR32(0x4284 + 0x400 * channel) = 1;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1);
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MCHBAR32(0x3400) = (slotrank << 2) | 0x8001;
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@ -1493,7 +1502,8 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank)
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MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 8;
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MCHBAR32(0x421c + 0x400 * channel) = 0x3e0;
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MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4);
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wait_428c(channel);
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@ -1525,7 +1535,10 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank)
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MCHBAR32(0x423c + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16);
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MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400;
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MCHBAR32(0x421c + 0x400 * channel) = 0x240;
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MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4);
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wait_428c(channel);
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}
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@ -1542,7 +1555,9 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank)
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MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16);
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MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400;
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MCHBAR32(0x4210 + 0x400 * channel) = 0x240;
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MCHBAR32(0x4284 + 0x400 * channel) = 1;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1);
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for (timC = 0; timC <= MAX_TIMC; timC++) {
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FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].
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@ -1661,7 +1676,9 @@ static void precharge(ramctr_timing * ctrl)
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MCHBAR32(0x420c + 0x400 * channel) =
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(slotrank << 24) | 0x360000;
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MCHBAR32(0x421c + 0x400 * channel) = 0;
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MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4);
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wait_428c(channel);
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}
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@ -1713,7 +1730,9 @@ static void precharge(ramctr_timing * ctrl)
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(slotrank << 24) | 0x360000;
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MCHBAR32(0x421c + 0x400 * channel) = 0;
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MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4);
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wait_428c(channel);
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}
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}
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@ -1740,7 +1759,9 @@ static void test_timB(ramctr_timing * ctrl, int channel, int slotrank)
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MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 4;
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MCHBAR32(0x4214 + 0x400 * channel) = 0;
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MCHBAR32(0x400 * channel + 0x4284) = 0x40001;
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// execute command queue
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MCHBAR32(0x400 * channel + 0x4284) = RUN_QUEUE_4284(2);
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wait_428c(channel);
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/* disable DQs on this slotrank */
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@ -1859,7 +1880,8 @@ static void adjust_high_timB(ramctr_timing * ctrl)
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MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x8;
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MCHBAR32(0x421c + 0x400 * channel) = 0x3e0;
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MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4);
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wait_428c(channel);
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@ -1886,7 +1908,9 @@ static void adjust_high_timB(ramctr_timing * ctrl)
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MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60008;
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MCHBAR32(0x4218 + 0x400 * channel) = 0;
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MCHBAR32(0x4284 + 0x400 * channel) = 0x80001;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(3);
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wait_428c(channel);
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FOR_ALL_LANES {
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u64 res = MCHBAR32(lane_registers[lane] +
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@ -1919,12 +1943,12 @@ static void write_op(ramctr_timing * ctrl, int channel)
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/* DRAM command ACT */
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MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003;
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MCHBAR32(0x4230 + 0x400 * channel) = 0x41001;
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MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000;
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MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0;
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MCHBAR32(0x4284 + 0x400 * channel) = 1;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1);
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wait_428c(channel);
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}
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@ -2003,7 +2027,9 @@ int write_training(ramctr_timing * ctrl)
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MCHBAR32(0x4200 + 0x400 * channel) = 0x60000;
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MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0;
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MCHBAR32(0x4284 + 0x400 * channel) = 1;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1);
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wait_428c(channel);
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}
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@ -2096,7 +2122,9 @@ static int test_320c(ramctr_timing * ctrl, int channel, int slotrank)
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MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400;
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MCHBAR32(0x421c + 0x400 * channel) = 0x240;
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MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4);
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wait_428c(channel);
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FOR_ALL_LANES {
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u32 r32 = MCHBAR32(0x4340 + 4 * lane + 0x400 * channel);
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@ -2159,12 +2187,12 @@ static void reprogram_320c(ramctr_timing * ctrl)
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/* DRAM command ZQCS */
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MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003;
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MCHBAR32(0x4230 + 0x400 * channel) = 0x41001;
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MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000;
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MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0;
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MCHBAR32(0x4284 + 0x400 * channel) = 1;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1);
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wait_428c(channel);
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MCHBAR32_OR(0x4020 + 0x400 * channel, 0x200000);
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}
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@ -2180,12 +2208,12 @@ static void reprogram_320c(ramctr_timing * ctrl)
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/* DRAM command ZQCS */
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MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003;
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MCHBAR32(0x4230 + 0x400 * channel) = 0x41001;
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MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000;
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MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0;
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MCHBAR32(0x4284 + 0x400 * channel) = 1;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1);
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wait_428c(channel);
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}
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@ -2373,7 +2401,8 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank,
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(slotrank << 24) | 0x360000;
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MCHBAR32(0x421c + 0x400 * channel) = 0;
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MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4);
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wait_428c(channel);
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@ -2467,7 +2496,9 @@ int discover_edges(ramctr_timing *ctrl)
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MCHBAR32(0x420c + 0x400 * channel) =
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(slotrank << 24) | 0x360000;
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MCHBAR32(0x421c + 0x400 * channel) = 0;
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MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4);
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wait_428c(channel);
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}
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@ -2522,7 +2553,9 @@ int discover_edges(ramctr_timing *ctrl)
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(slotrank << 24) | 0x360000;
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MCHBAR32(0x421c + 0x400 * channel) = 0;
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MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4);
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wait_428c(channel);
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}
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@ -2655,7 +2688,10 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel,
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(slotrank << 24) | 0x60400;
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MCHBAR32(0x421c + 0x400 * channel) = 0;
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MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) =
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RUN_QUEUE_4284(4);
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wait_428c(channel);
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FOR_ALL_LANES {
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volatile u32 tmp;
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@ -2774,7 +2810,9 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank)
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MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400;
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MCHBAR32(0x421c + 0x400 * channel) = 0;
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MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001;
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// execute command queue
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MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4);
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wait_428c(channel);
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}
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@ -2940,31 +2978,38 @@ int channel_test(ramctr_timing *ctrl)
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MCHBAR32(0x4d40 + 4 * lane) = 0;
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}
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wait_428c(channel);
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/* DRAM command ACT */
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MCHBAR32(0x4220 + (channel << 10)) = 0x0001f006;
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MCHBAR32(0x4230 + (channel << 10)) = 0x0028a004;
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MCHBAR32(0x4200 + (channel << 10)) =
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0x00060000 | (slotrank << 24);
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MCHBAR32(0x4210 + (channel << 10)) = 0x00000244;
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/* DRAM command WR */
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MCHBAR32(0x4224 + (channel << 10)) = 0x0001f201;
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MCHBAR32(0x4234 + (channel << 10)) = 0x08281064;
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MCHBAR32(0x4204 + (channel << 10)) =
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0x00000000 | (slotrank << 24);
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MCHBAR32(0x4214 + (channel << 10)) = 0x00000242;
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/* DRAM command RD */
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MCHBAR32(0x4228 + (channel << 10)) = 0x0001f105;
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MCHBAR32(0x4238 + (channel << 10)) = 0x04281064;
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MCHBAR32(0x4208 + (channel << 10)) =
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0x00000000 | (slotrank << 24);
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MCHBAR32(0x4218 + (channel << 10)) = 0x00000242;
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/* DRAM command PRE */
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MCHBAR32(0x422c + (channel << 10)) = 0x0001f002;
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MCHBAR32(0x423c + (channel << 10)) = 0x00280c01;
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MCHBAR32(0x420c + (channel << 10)) =
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0x00060400 | (slotrank << 24);
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MCHBAR32(0x421c + (channel << 10)) = 0x00000240;
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MCHBAR32(0x4284 + (channel << 10)) = 0x000c0001;
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// execute command queue
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MCHBAR32(0x4284 + (channel << 10)) = RUN_QUEUE_4284(4);
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wait_428c(channel);
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FOR_ALL_LANES
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if (MCHBAR32(0x4340 + (channel << 10) + 4 * lane)) {
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