sb/intel/i82801jx/fadt.c: Reorder statements
Change the order of the assignments to match that of i82801ix. This changes the binary but the effective result should be the same. Change-Id: Ib190781f26f82f339eaf8039de459376ac0e3a5e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -13,6 +13,16 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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struct southbridge_intel_i82801jx_config *chip = dev->chip_info;
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u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
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fadt->sci_int = 0x9;
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if (permanent_smi_handler()) {
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fadt->smi_cmd = APM_CNT;
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fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
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fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
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fadt->pstate_cnt = APM_CNT_PST_CONTROL;
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fadt->cst_cnt = APM_CNT_CST_CONTROL;
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}
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fadt->pm1a_evt_blk = pmbase;
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fadt->pm1b_evt_blk = 0x0;
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fadt->pm1a_cnt_blk = pmbase + 0x4;
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@ -29,6 +39,25 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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fadt->gpe0_blk_len = 16;
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fadt->gpe1_blk_len = 0;
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fadt->gpe1_base = 0;
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fadt->p_lvl2_lat = 1;
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fadt->p_lvl3_lat = chip->c3_latency;
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fadt->flush_size = 0;
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fadt->flush_stride = 0;
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fadt->duty_offset = 1;
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if (chip->p_cnt_throttling_supported)
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fadt->duty_width = 3;
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else
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fadt->duty_width = 0;
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fadt->day_alrm = 0xd;
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fadt->mon_alrm = 0x00;
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fadt->century = 0x32;
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fadt->iapc_boot_arch = 0x03;
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fadt->flags = (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED
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| ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE
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| ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_RESET_REGISTER
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| ACPI_FADT_C2_MP_SUPPORTED);
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if (chip->docking_supported)
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fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
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fadt->reset_reg.space_id = 1;
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fadt->reset_reg.bit_width = 8;
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@ -93,34 +122,4 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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fadt->x_gpe1_blk.access_size = 0;
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fadt->x_gpe1_blk.addrl = 0x0;
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fadt->x_gpe1_blk.addrh = 0x0;
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fadt->day_alrm = 0xd;
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fadt->mon_alrm = 0x00;
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fadt->century = 0x32;
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fadt->sci_int = 0x9;
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if (permanent_smi_handler()) {
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fadt->smi_cmd = APM_CNT;
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fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
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fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
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fadt->cst_cnt = APM_CNT_CST_CONTROL;
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fadt->pstate_cnt = APM_CNT_PST_CONTROL;
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}
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fadt->p_lvl2_lat = 1;
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fadt->p_lvl3_lat = chip->c3_latency;
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fadt->flush_size = 0;
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fadt->flush_stride = 0;
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fadt->duty_offset = 1;
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if (chip->p_cnt_throttling_supported)
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fadt->duty_width = 3;
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else
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fadt->duty_width = 0;
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fadt->iapc_boot_arch = 0x03;
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fadt->flags = (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED
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| ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE
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| ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_RESET_REGISTER
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| ACPI_FADT_C2_MP_SUPPORTED);
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if (chip->docking_supported)
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fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
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}
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