From 9cffe25ce0b06a19e3e18978ea83e006f64886a2 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Wed, 20 Sep 2017 17:09:19 -0600 Subject: [PATCH] google/kahlee: Fix GPIO ASL Use a single define and set the CROS GPIO ASL device to match the Stoney Ridge GPIO HID. Update the GPIO number to 142. Also, add a DDN field in the GPIO ASL. This addresses the TEST indicated below. BUG=b:65597554 BRANCH=none TEST=grep ^ /sys/devices/platform/chromeos_acpi/GPIO.*/* reports AMD0030. Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/21614 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/kahlee/acpi/carrizo_fch.asl | 9 ++++++--- src/mainboard/google/kahlee/chromeos.c | 6 +++--- src/soc/amd/stoneyridge/include/soc/gpio.h | 8 +++++--- 3 files changed, 14 insertions(+), 9 deletions(-) diff --git a/src/mainboard/google/kahlee/acpi/carrizo_fch.asl b/src/mainboard/google/kahlee/acpi/carrizo_fch.asl index 04f563eb12..9bf7decb49 100644 --- a/src/mainboard/google/kahlee/acpi/carrizo_fch.asl +++ b/src/mainboard/google/kahlee/acpi/carrizo_fch.asl @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include + Device (AAHB) { Name (_HID, "AAHB0000") @@ -30,9 +32,10 @@ Device (AAHB) Device (GPIO) { - Name (_HID, "AMD0030") - Name (_CID, "AMD0030") - Name(_UID, 0) + Name (_HID, GPIO_DEVICE_NAME) + Name (_CID, GPIO_DEVICE_NAME) + Name (_UID, 0) + Name (_DDN, GPIO_DEVICE_DESC) Name (_CRS, ResourceTemplate() { diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index 156614bbb8..4c152ba0e5 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -21,7 +21,7 @@ #include /* SPI Write protect */ -#define CROS_WP_GPIO GPIO_122 +#define CROS_WP_GPIO GPIO_142 void fill_lb_gpios(struct lb_gpios *gpios) { @@ -40,8 +40,8 @@ int get_write_protect_state(void) } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(CROS_WP_GPIO, GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 6378ca8580..734074aad6 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -16,11 +16,13 @@ #ifndef __STONEYRIDGE_GPIO_H__ #define __STONEYRIDGE_GPIO_H__ +#define GPIO_DEVICE_NAME "AMD0030" +#define GPIO_DEVICE_DESC "GPIO Controller" + +#ifndef __ACPI__ #include #include -#define CROS_GPIO_DEVICE_NAME "AmdKern" - #define GPIO_PIN_STS (1 << 16) #define GPIO_PULLUP_ENABLE (1 << 20) #define GPIO_PULLDOWN_ENABLE (1 << 21) @@ -132,5 +134,5 @@ #define GPIO_148 148 typedef uint32_t gpio_t; - +#endif /* __ACPI__ */ #endif /* __STONEYRIDGE_GPIO_H__ */