fsp_baytrail: Add full support for iosf access in reg_script
Add all needed functions to fsp_baytrail so that reg_script can do full iosf access. To keep it simple, this patch synchronises iosf access between baytrail and fsp_baytrail. Change-Id: Ic7f52d7d90c0fe3560fa5a5d96f7fc15062d66d1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/13742 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Werner Zeh
Martin Roth
parent
a05d033226
commit
9d0215363d
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@ -290,7 +290,8 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries);
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REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_)
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#if CONFIG_SOC_INTEL_BAYTRAIL
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#if IS_ENABLED(CONFIG_SOC_INTEL_BAYTRAIL) || \
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IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL)
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/*
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* IO Sideband Function
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*/
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@ -310,7 +311,7 @@ const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries);
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REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_)
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#define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \
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REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_)
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#endif /* CONFIG_SOC_INTEL_BAYTRAIL */
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#endif /* CONFIG_SOC_INTEL_BAYTRAIL || CONFIG_SOC_INTEL_FSP_BAYTRAIL*/
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/*
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* CPU Model Specific Register
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@ -26,7 +26,10 @@
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#include <cpu/x86/msr.h>
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#endif
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#if CONFIG_SOC_INTEL_BAYTRAIL
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#define HAS_IOSF (IS_ENABLED(CONFIG_SOC_INTEL_BAYTRAIL) || \
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IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL))
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#if HAS_IOSF
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#include <soc/iosf.h> /* TODO: wrap in <soc/reg_script.h, remove #ifdef? */
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#endif
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@ -233,7 +236,7 @@ static void reg_script_write_res(struct reg_script_context *ctx)
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reg_script_set_step(ctx, step);
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}
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#if CONFIG_SOC_INTEL_BAYTRAIL
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#if HAS_IOSF
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static uint32_t reg_script_read_iosf(struct reg_script_context *ctx)
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{
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const struct reg_script *step = reg_script_get_step(ctx);
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@ -363,7 +366,7 @@ static void reg_script_write_iosf(struct reg_script_context *ctx)
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break;
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}
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}
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#endif
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#endif /* HAS_IOSF */
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static uint64_t reg_script_read_msr(struct reg_script_context *ctx)
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@ -435,10 +438,10 @@ static uint64_t reg_script_read(struct reg_script_context *ctx)
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return reg_script_read_res(ctx);
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case REG_SCRIPT_TYPE_MSR:
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return reg_script_read_msr(ctx);
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#if CONFIG_SOC_INTEL_BAYTRAIL
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#if HAS_IOSF
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case REG_SCRIPT_TYPE_IOSF:
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return reg_script_read_iosf(ctx);
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#endif
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#endif /* HAS_IOSF */
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default:
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#ifndef __PRE_RAM__
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{
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@ -478,11 +481,11 @@ static void reg_script_write(struct reg_script_context *ctx)
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case REG_SCRIPT_TYPE_MSR:
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reg_script_write_msr(ctx);
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break;
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#if CONFIG_SOC_INTEL_BAYTRAIL
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#if HAS_IOSF
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case REG_SCRIPT_TYPE_IOSF:
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reg_script_write_iosf(ctx);
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break;
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#endif
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#endif /* HAS_IOSF */
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default:
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#ifndef __PRE_RAM__
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{
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google, Inc.
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* Copyright (C) 2016 Siemens AG
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -51,6 +52,10 @@
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#define MDR_REG 0xd4
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#define MCRX_REG 0xd8
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uint32_t iosf_aunit_read(int reg);
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void iosf_aunit_write(int reg, uint32_t val);
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uint32_t iosf_cpu_bus_read(int reg);
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void iosf_cpu_bus_write(int reg, uint32_t val);
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uint32_t iosf_bunit_read(int reg);
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void iosf_bunit_write(int reg, uint32_t val);
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uint32_t iosf_dunit_read(int reg);
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@ -59,25 +64,120 @@ void iosf_dunit_write(int reg, uint32_t val);
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uint32_t iosf_dunit_ch0_read(int reg);
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uint32_t iosf_dunit_ch1_read(int reg);
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uint32_t iosf_punit_read(int reg);
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void iosf_punit_write(int reg, uint32_t val);
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uint32_t iosf_usbphy_read(int reg);
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void iosf_usbphy_write(int reg, uint32_t val);
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uint32_t iosf_ushphy_read(int reg);
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void iosf_ushphy_write(int reg, uint32_t val);
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uint32_t iosf_sec_read(int reg);
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void iosf_sec_write(int reg, uint32_t val);
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uint32_t iosf_port45_read(int reg);
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void iosf_port45_write(int reg, uint32_t val);
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uint32_t iosf_port46_read(int reg);
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void iosf_port46_write(int reg, uint32_t val);
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uint32_t iosf_port47_read(int reg);
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void iosf_port47_write(int reg, uint32_t val);
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uint32_t iosf_port55_read(int reg);
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void iosf_port55_write(int reg, uint32_t val);
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uint32_t iosf_port58_read(int reg);
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void iosf_port58_write(int reg, uint32_t val);
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uint32_t iosf_port59_read(int reg);
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void iosf_port59_write(int reg, uint32_t val);
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uint32_t iosf_port5a_read(int reg);
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void iosf_port5a_write(int reg, uint32_t val);
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uint32_t iosf_lpss_read(int reg);
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void iosf_lpss_write(int reg, uint32_t val);
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uint32_t iosf_ccu_read(int reg);
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void iosf_ccu_write(int reg, uint32_t val);
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uint32_t iosf_score_read(int reg);
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void iosf_score_write(int reg, uint32_t val);
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uint32_t iosf_scc_read(int reg);
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void iosf_scc_write(int reg, uint32_t val);
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uint32_t iosf_porta2_read(int reg);
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void iosf_porta2_write(int reg, uint32_t val);
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uint32_t iosf_ssus_read(int reg);
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void iosf_ssus_write(int reg, uint32_t val);
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/* IOSF ports. */
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#define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */
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#define IOSF_PORT_SYSMEMC 0x01 /* System Memory Controller */
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#define IOSF_PORT_DUNIT_CH0 0x07 /* DUNIT Channel 0 */
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#define IOSF_PORT_CPU_BUS 0x02 /* CPU Bus Interface Controller */
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#define IOSF_PORT_BUNIT 0x03 /* System Memory Arbiter/Bunit */
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#define IOSF_PORT_PMC 0x04 /* Power Management Controller */
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#define IOSF_PORT_GFX 0x06 /* Graphics Adapter */
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#define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */
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#define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */
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#define IOSF_PORT_USBPHY 0x43 /* USB PHY */
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#define IOSF_PORT_SEC 0x44 /* SEC */
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#define IOSF_PORT_0x45 0x45
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#define IOSF_PORT_0x46 0x46
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#define IOSF_PORT_0x47 0x47
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#define IOSF_PORT_SCORE 0x48 /* SCORE */
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#define IOSF_PORT_0x55 0x55
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#define IOSF_PORT_0x58 0x58
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#define IOSF_PORT_0x59 0x59
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#define IOSF_PORT_0x5a 0x5a
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#define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */
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#define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */
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#define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */
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#define IOSF_PORT_0xa2 0xa2
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#define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */
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#define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */
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#define IOSF_PORT_SSUS 0xa8 /* SUS */
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#define IOSF_PORT_CCU 0xa9 /* Clock control unit. */
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/* Read and write opcodes differ per port. */
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#define IOSF_OP_READ_AUNIT 0x10
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#define IOSF_OP_WRITE_AUNIT (IOSF_OP_READ_AUNIT | 1)
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#define IOSF_OP_READ_SYSMEMC 0x10
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#define IOSF_OP_WRITE_SYSMEMC (IOSF_OP_READ_SYSMEMC | 1)
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#define IOSF_OP_READ_CPU_BUS 0x10
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#define IOSF_OP_WRITE_CPU_BUS (IOSF_OP_READ_CPU_BUS | 1)
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#define IOSF_OP_READ_BUNIT 0x10
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#define IOSF_OP_WRITE_BUNIT (IOSF_OP_READ_BUNIT | 1)
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#define IOSF_OP_READ_PMC 0x06
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#define IOSF_OP_WRITE_PMC (IOSF_OP_READ_PMC | 1)
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#define IOSF_OP_READ_GFX 0x00
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#define IOSF_OP_WRITE_GFX (IOSF_OP_READ_GFX | 1)
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#define IOSF_OP_READ_SYSMEMIO 0x06
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#define IOSF_OP_WRITE_SYSMEMIO (IOSF_OP_READ_SYSMEMIO | 1)
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#define IOSF_OP_READ_USBPHY 0x06
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#define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1)
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#define IOSF_OP_READ_SEC 0x04
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#define IOSF_OP_WRITE_SEC (IOSF_OP_READ_SEC | 1)
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#define IOSF_OP_READ_0x45 0x06
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#define IOSF_OP_WRITE_0x45 (IOSF_OP_READ_0x45 | 1)
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#define IOSF_OP_READ_0x46 0x06
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#define IOSF_OP_WRITE_0x46 (IOSF_OP_READ_0x46 | 1)
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#define IOSF_OP_READ_0x47 0x06
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#define IOSF_OP_WRITE_0x47 (IOSF_OP_READ_0x47 | 1)
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#define IOSF_OP_READ_SCORE 0x06
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#define IOSF_OP_WRITE_SCORE (IOSF_OP_READ_SCORE | 1)
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#define IOSF_OP_READ_0x55 0x04
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#define IOSF_OP_WRITE_0x55 (IOSF_OP_READ_0x55 | 1)
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#define IOSF_OP_READ_0x58 0x06
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#define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1)
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#define IOSF_OP_READ_0x59 0x06
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#define IOSF_OP_WRITE_0x59 (IOSF_OP_READ_0x59 | 1)
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#define IOSF_OP_READ_0x5a 0x04
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#define IOSF_OP_WRITE_0x5a (IOSF_OP_READ_0x5a | 1)
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#define IOSF_OP_READ_USHPHY 0x06
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#define IOSF_OP_WRITE_USHPHY (IOSF_OP_READ_USHPHY | 1)
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#define IOSF_OP_READ_SCC 0x06
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#define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1)
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#define IOSF_OP_READ_LPSS 0x06
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#define IOSF_OP_WRITE_LPSS (IOSF_OP_READ_LPSS | 1)
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#define IOSF_OP_READ_0xa2 0x06
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#define IOSF_OP_WRITE_0xa2 (IOSF_OP_READ_0xa2 | 1)
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#define IOSF_OP_READ_SATAPHY 0x00
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#define IOSF_OP_WRITE_SATAPHY (IOSF_OP_READ_SATAPHY | 1)
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#define IOSF_OP_READ_PCIEPHY 0x00
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#define IOSF_OP_WRITE_PCIEPHY (IOSF_OP_READ_PCIEPHY | 1)
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#define IOSF_OP_READ_SSUS 0x10
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#define IOSF_OP_WRITE_SSUS (IOSF_OP_READ_SSUS | 1)
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#define IOSF_OP_READ_CCU 0x06
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#define IOSF_OP_WRITE_CCU (IOSF_OP_READ_CCU | 1)
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/*
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* BUNIT Registers.
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@ -94,10 +194,18 @@ void iosf_lpss_write(int reg, uint32_t val);
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#define BUNIT_BMBOUND_HI 0x26
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#define BUNIT_MMCONF_REG 0x27
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/* The SMMRR registers define the SMM region in MiB granularity. */
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#define BUNIT_SMRCP 0x2b
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#define BUNIT_SMRRAC 0x2c
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#define BUNIT_SMRWAC 0x2d
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#define BUNIT_SMRRL 0x2e
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#define BUNIT_SMRRH 0x2f
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# define BUNIT_SMRR_ENABLE (1 << 31)
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/* SA ID bits. */
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#define SAI_IA_UNTRUSTED (1 << 0)
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#define SAI_IA_SMM (1 << 2)
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#define SAI_IA_BOOT (1 << 4)
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/*
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* DUNIT Registers.
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*/
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@ -116,6 +224,46 @@ void iosf_lpss_write(int reg, uint32_t val);
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# define DTR0_SPEED_1333 0x02
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# define DTR0_SPEED_1600 0x03
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/*
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* PUNIT Registers
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*/
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#define SB_BIOS_CONFIG 0x06
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# define SB_BIOS_CONFIG_ECC_EN (1 << 31)
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# define SB_BIOS_CONFIG_DUAL_CH_DIS (1 << 30)
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# define SB_BIOS_CONFIG_EFF_ECC (1 << 29)
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# define SB_BIOS_CONFIG_EFF_DUAL_CH_DIS (1 << 28)
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# define SB_BIOS_CONFIG_PERF_MODE (1 << 17)
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# define SB_BIOS_CONFIG_PDM_MODE (1 << 16)
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# define SB_BIOS_CONFIG_DDRIO_PWRGATE (1 << 8)
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# define SB_BIOS_CONFIG_GFX_TURBO_DIS (1 << 7)
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# define SB_BIOS_CONFIG_PS2_EN_VNN (1 << 3)
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# define SB_BIOS_CONFIG_PS2_EN_VCC (1 << 2)
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# define SB_BIOS_CONFIG_PCIE_PLLOFFOK (1 << 1)
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# define SB_BIOS_CONFIG_USB_CACHING_EN (1 << 0)
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#define BIOS_RESET_CPL 0x05
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# define BIOS_RESET_CPL_ALL_DONE (1 << 1)
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# define BIOS_RESET_CPL_RESET_DONE (1 << 0)
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#define PUNIT_PWRGT_CONTROL 0x60
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#define PUNIT_PWRGT_STATUS 0x61
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#define PUNIT_GPU_EC_VIRUS 0xd2
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#define PUNIT_SOC_POWER_BUDGET 0x02
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#define PUNIT_SOC_ENERGY_CREDIT 0x03
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#define PUNIT_PTMC 0x80
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#define PUNIT_GFXT 0x88
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#define PUNIT_VEDT 0x89
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#define PUNIT_ISPT 0x8c
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#define PUNIT_PTPS 0xb2
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#define PUNIT_TE_AUX0 0xb5
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#define PUNIT_TE_AUX1 0xb6
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#define PUNIT_TE_AUX2 0xb7
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#define PUNIT_TE_AUX3 0xb8
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#define PUNIT_TTE_VRIccMax 0xb9
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#define PUNIT_TTE_VRHot 0xba
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#define PUNIT_TTE_XXPROCHOT 0xbb
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#define PUNIT_TTE_SLM0 0xbc
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#define PUNIT_TTE_SLM1 0xbd
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#define PUNIT_TTE_SWT 0xbf
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/*
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* LPSS Registers
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@ -188,4 +336,11 @@ void iosf_lpss_write(int reg, uint32_t val);
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#define USHPHY_REE_DAC_CONTROL 0x80b8
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#define USHPHY_CDN_U1_POWER_STATE_DEF 0x0000
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/*
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* LPE Registers
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*/
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#define LPE_PCICFGCTR1 0x0500
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# define LPE_PCICFGCTR1_PCI_CFG_DIS (1 << 0)
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# define LPE_PCICFGCTR1_ACPI_INT_EN (1 << 1)
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#endif /* _BAYTRAIL_IOSF_H_ */
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@ -3,6 +3,7 @@
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*
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* Copyright (C) 2013 Google, Inc.
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* Copyright (C) 2014 Sage Electronic Engineering, LLC.
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* Copyright (C) 2016 Siemens AG
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -93,6 +94,36 @@ void iosf_dunit_write(int reg, uint32_t val)
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iosf_write_port(IOSF_WRITE(SYSMEMC), reg, val);
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}
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uint32_t iosf_punit_read(int reg)
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{
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return iosf_read_port(IOSF_READ(PMC), reg);
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}
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void iosf_punit_write(int reg, uint32_t val)
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{
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iosf_write_port(IOSF_WRITE(PMC), reg, val);
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}
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uint32_t iosf_usbphy_read(int reg)
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{
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return iosf_read_port(IOSF_READ(USBPHY), reg);
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}
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void iosf_usbphy_write(int reg, uint32_t val)
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{
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return iosf_write_port(IOSF_WRITE(USBPHY), reg, val);
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}
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uint32_t iosf_ushphy_read(int reg)
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{
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return iosf_read_port(IOSF_READ(USHPHY), reg);
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}
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void iosf_ushphy_write(int reg, uint32_t val)
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{
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return iosf_write_port(IOSF_WRITE(USHPHY), reg, val);
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}
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uint32_t iosf_lpss_read(int reg)
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{
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return iosf_read_port(IOSF_READ(LPSS), reg);
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@ -102,3 +133,153 @@ void iosf_lpss_write(int reg, uint32_t val)
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{
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return iosf_write_port(IOSF_WRITE(LPSS), reg, val);
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}
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uint32_t iosf_ccu_read(int reg)
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{
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return iosf_read_port(IOSF_READ(CCU), reg);
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}
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||||
|
||||
void iosf_ccu_write(int reg, uint32_t val)
|
||||
{
|
||||
return iosf_write_port(IOSF_WRITE(CCU), reg, val);
|
||||
}
|
||||
|
||||
uint32_t iosf_score_read(int reg)
|
||||
{
|
||||
return iosf_read_port(IOSF_READ(SCORE), reg);
|
||||
}
|
||||
|
||||
void iosf_score_write(int reg, uint32_t val)
|
||||
{
|
||||
return iosf_write_port(IOSF_WRITE(SCORE), reg, val);
|
||||
}
|
||||
|
||||
uint32_t iosf_scc_read(int reg)
|
||||
{
|
||||
return iosf_read_port(IOSF_READ(SCC), reg);
|
||||
}
|
||||
|
||||
void iosf_scc_write(int reg, uint32_t val)
|
||||
{
|
||||
return iosf_write_port(IOSF_WRITE(SCC), reg, val);
|
||||
}
|
||||
|
||||
uint32_t iosf_aunit_read(int reg)
|
||||
{
|
||||
return iosf_read_port(IOSF_READ(AUNIT), reg);
|
||||
}
|
||||
|
||||
void iosf_aunit_write(int reg, uint32_t val)
|
||||
{
|
||||
return iosf_write_port(IOSF_WRITE(AUNIT), reg, val);
|
||||
}
|
||||
|
||||
uint32_t iosf_cpu_bus_read(int reg)
|
||||
{
|
||||
return iosf_read_port(IOSF_READ(CPU_BUS), reg);
|
||||
}
|
||||
|
||||
void iosf_cpu_bus_write(int reg, uint32_t val)
|
||||
{
|
||||
return iosf_write_port(IOSF_WRITE(CPU_BUS), reg, val);
|
||||
}
|
||||
|
||||
uint32_t iosf_sec_read(int reg)
|
||||
{
|
||||
return iosf_read_port(IOSF_READ(SEC), reg);
|
||||
}
|
||||
|
||||
void iosf_sec_write(int reg, uint32_t val)
|
||||
{
|
||||
return iosf_write_port(IOSF_WRITE(SEC), reg, val);
|
||||
}
|
||||
|
||||
uint32_t iosf_port45_read(int reg)
|
||||
{
|
||||
return iosf_read_port(IOSF_READ(0x45), reg);
|
||||
}
|
||||
|
||||
void iosf_port45_write(int reg, uint32_t val)
|
||||
{
|
||||
return iosf_write_port(IOSF_WRITE(0x45), reg, val);
|
||||
}
|
||||
|
||||
uint32_t iosf_port46_read(int reg)
|
||||
{
|
||||
return iosf_read_port(IOSF_READ(0x46), reg);
|
||||
}
|
||||
|
||||
void iosf_port46_write(int reg, uint32_t val)
|
||||
{
|
||||
return iosf_write_port(IOSF_WRITE(0x46), reg, val);
|
||||
}
|
||||
|
||||
uint32_t iosf_port47_read(int reg)
|
||||
{
|
||||
return iosf_read_port(IOSF_READ(0x47), reg);
|
||||
}
|
||||
|
||||
void iosf_port47_write(int reg, uint32_t val)
|
||||
{
|
||||
return iosf_write_port(IOSF_WRITE(0x47), reg, val);
|
||||
}
|
||||
|
||||
uint32_t iosf_port55_read(int reg)
|
||||
{
|
||||
return iosf_read_port(IOSF_READ(0x55), reg);
|
||||
}
|
||||
|
||||
void iosf_port55_write(int reg, uint32_t val)
|
||||
{
|
||||
return iosf_write_port(IOSF_WRITE(0x55), reg, val);
|
||||
}
|
||||
|
||||
uint32_t iosf_port58_read(int reg)
|
||||
{
|
||||
return iosf_read_port(IOSF_READ(0x58), reg);
|
||||
}
|
||||
|
||||
void iosf_port58_write(int reg, uint32_t val)
|
||||
{
|
||||
return iosf_write_port(IOSF_WRITE(0x58), reg, val);
|
||||
}
|
||||
|
||||
uint32_t iosf_port59_read(int reg)
|
||||
{
|
||||
return iosf_read_port(IOSF_READ(0x59), reg);
|
||||
}
|
||||
|
||||
void iosf_port59_write(int reg, uint32_t val)
|
||||
{
|
||||
return iosf_write_port(IOSF_WRITE(0x59), reg, val);
|
||||
}
|
||||
|
||||
uint32_t iosf_port5a_read(int reg)
|
||||
{
|
||||
return iosf_read_port(IOSF_READ(0x5a), reg);
|
||||
}
|
||||
|
||||
void iosf_port5a_write(int reg, uint32_t val)
|
||||
{
|
||||
return iosf_write_port(IOSF_WRITE(0x5a), reg, val);
|
||||
}
|
||||
|
||||
uint32_t iosf_porta2_read(int reg)
|
||||
{
|
||||
return iosf_read_port(IOSF_READ(0xa2), reg);
|
||||
}
|
||||
|
||||
void iosf_porta2_write(int reg, uint32_t val)
|
||||
{
|
||||
return iosf_write_port(IOSF_WRITE(0xa2), reg, val);
|
||||
}
|
||||
|
||||
uint32_t iosf_ssus_read(int reg)
|
||||
{
|
||||
return iosf_read_port(IOSF_READ(SSUS), reg);
|
||||
}
|
||||
|
||||
void iosf_ssus_write(int reg, uint32_t val)
|
||||
{
|
||||
return iosf_write_port(IOSF_WRITE(SSUS), reg, val);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue