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soc/intel/{glk,apl}: ensure C1E is disabled after S3 resume 

C1E is disabled by the kernel driver intel_idle at boot.  This does not
address the S3 resume case, so we lose state and C1E is enabled after S3
resume.

Disable C1E for GLK as it is for APL.  This gives a coherent state before
and after S3 resume.

TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3
resume with bit [1] set to zero (0x20005d).

Change-Id: I437cbaca75c539c2bc5cd801ab8df907e7447d10
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/27019
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Cole Nelson 2018-06-12 10:02:49 -07:00 committed by Patrick Georgi
parent 2b69b21c2d
commit 9d0950f154
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/apollolake/cpu.c
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@ -53,11 +53,11 @@ static const struct reg_script core_msr_script[] = {
/* Power Management I/O base address for I/O trapping to C-states */ /* Power Management I/O base address for I/O trapping to C-states */
REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE, REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE,
(ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))), (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))),
/* Disable C1E */
REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),
/* Disable support for MONITOR and MWAIT instructions */ /* Disable support for MONITOR and MWAIT instructions */
REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0), REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0),
#endif #endif
/* Disable C1E */
REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0),
/* /*
* Enable and Lock the Advanced Encryption Standard (AES-NI) * Enable and Lock the Advanced Encryption Standard (AES-NI)
* feature register * feature register