Fixes from AMD. Tested to build on rumba and olpc, and builds.
Tested to booting linux on olpc, and boots. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
1f96360315
commit
9d0b30dd2b
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@ -90,7 +90,7 @@ pcideadlock(void)
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* Exit:
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* Modified:
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*
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/****************************************************************************/
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****************************************************************************/
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void bug784(void)
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{
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@ -150,117 +150,102 @@ void eng1398(void)
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wrmsr(MC_GLD_MSR_PM, msr);
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}
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/***************************************************************************
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*
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* CPUbugIAENG2900
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*
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* Clear Quest IAENG00002900, VSS 118.150
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*
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* BTB issue causes blue screen in windows, but the fix is required
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* for all operating systems.
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*
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* Entry:
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* Exit:
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* Modified:
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*
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**************************************************************************/
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void
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eng2900(void){
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printk_err(" NOT DOING eng2900: only shown to be a windows problem\n");
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#if 0
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eng2900(void)
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{
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msr_t msr;
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;**************************************************************************
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;*
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;* CPUbugIAENG2900
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;*
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;* Clear Quest IAENG00002900, VSS 118.150
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;*
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;* BTB issue causes blue screen in windows.
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;*
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;* Entry:
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;* Exit:
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;* Modified:
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;*
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;**************************************************************************
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CPUbugIAENG2900 PROC NEAR PUBLIC
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pushad
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printk_debug("CPU_BUG:%s\n", __FUNCTION__);
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/* Clear bit 43, disables the sysenter/sysexit in CPUID3 */
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msr = rdmsr(0x3003);
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msr.hi &= 0xFFFFF7FF;
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wrmsr(0x3003, msr);
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; Clear bit 43, disables the sysenter/sysexit in CPUID3
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mov ecx, 3003h
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RDMSR
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and edx, 0FFFFF7FFh
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WRMSR
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/* change this value to zero if you need to disable this BTB SWAPSiF. */
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if (1) {
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mov cx, TOKEN_BTB_2900_SWAPSIF_ENABLE
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NOSTACK bx, GetNVRAMValueBX
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cmp ax, TVALUE_ENABLE
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jne bug2900exit
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/* Disable enable_actions in DIAGCTL while setting up GLCP */
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msr.hi = 0;
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msr.lo = 0;
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wrmsr(MSR_GLCP + 0x005f, msr);
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/* Changing DBGCLKCTL register to GeodeLink */
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msr.hi = 0;
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msr.lo = 0;
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wrmsr(MSR_GLCP + 0x0016, msr);
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;Disable enable_actions in DIAGCTL while setting up GLCP
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mov ecx, MSR_GLCP + 005fh
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xor edx, edx
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xor eax, eax
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WRMSR
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msr.hi = 0;
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msr.lo = 2;
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wrmsr(MSR_GLCP + 0x0016, msr);
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;Changing DBGCLKCTL register to GeodeLink
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mov ecx, MSR_GLCP + 0016h
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xor edx, edx
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xor eax, eax
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WRMSR
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/* The code below sets up the CPU to stall for 4 GeodeLink
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* clocks when CPU is snooped. Because setting XSTATE to 0
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* overrides any other XSTATE action, the code will always
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* stall for 4 GeodeLink clocks after a snoop request goes
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* away even if it occured a clock or two later than a
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* different snoop; the stall signal will never 'glitch high'
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* for only one or two CPU clocks with this code.
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*/
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mov ecx, MSR_GLCP + 0016h
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xor edx, edx
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mov eax, 02h
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WRMSR
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/* Send mb0 port 3 requests to upper GeodeLink diag bits
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[63:32] */
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msr.hi = 0;
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msr.lo = 0x80338041;
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wrmsr(MSR_GLIU0 + 0x2005, msr);
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;The code below sets up the RedCloud to stall for 4 GeodeLink clocks when CPU is snooped.
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;Because setting XSTATE to 0 overrides any other XSTATE action, the code will always
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;stall for 4 GeodeLink clocks after a snoop request goes away even if it occured a clock or two
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;later than a different snoop; the stall signal will never 'glitch high' for
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;only one or two CPU clocks with this code.
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/* set5m watches request ready from mb0 to CPU (snoop) */
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msr.hi = 0x5ad68000;
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msr.lo = 0;
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wrmsr(MSR_GLCP + 0x0045, msr);
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;Send mb0 port 3 requests to upper GeodeLink diag bits [63:32]
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mov ecx, MSR_GLIU0 + 2005h
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xor edx, edx
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mov eax, 80338041h
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WRMSR
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/* SET4M will be high when state is idle (XSTATE=11) */
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msr.hi = 0;
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msr.lo = 0x0140;
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wrmsr(MSR_GLCP + 0x0044, msr);
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;set5m watches request ready from mb0 to CPU (snoop)
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mov ecx, MSR_GLCP + 0045h
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mov edx, 5ad68000h
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xor eax, eax
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WRMSR
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/* SET5n to watch for processor stalled state */
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msr.hi = 0x2000;
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msr.lo = 0;
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wrmsr(MSR_GLCP + 0x004D, msr);
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;SET4M will be high when state is idle (XSTATE=11)
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mov ecx, MSR_GLCP + 0044h
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xor edx, edx
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mov eax, 0140h
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WRMSR
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/* Writing action number 13: XSTATE=0 to occur when CPU is
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snooped unless we're stalled */
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msr.hi = 0;
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msr.lo = 0x00400000;
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wrmsr(MSR_GLCP + 0x0075, msr);
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;SET5n to watch for processor stalled state
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mov ecx, MSR_GLCP + 004Dh
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mov edx, 2000h
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xor eax, eax
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WRMSR
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/* Writing action number 11: inc XSTATE every GeodeLink clock
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unless we're idle */
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msr.hi = 0;
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msr.lo = 0x30000;
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wrmsr(MSR_GLCP + 0x0073, msr);
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;Writing action number 13: XSTATE=0 to occur when CPU is snooped unless we're stalled
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mov ecx, MSR_GLCP + 0075h
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xor edx, edx
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mov eax, 00400000h
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WRMSR
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/* Writing action number 5: STALL_CPU_PIPE when exitting idle
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state or not in idle state */
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msr.hi = 0;
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msr.lo = 0x00430000;
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wrmsr(MSR_GLCP + 0x006D, msr);
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;Writing action number 11: inc XSTATE every GeodeLink clock unless we're idle
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mov ecx, MSR_GLCP + 0073h
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xor edx, edx
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mov eax, 30000h
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WRMSR
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;Writing action number 5: STALL_CPU_PIPE when exitting idle state or not in idle state
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mov ecx, MSR_GLCP + 006Dh
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xor edx, edx
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mov eax, 00430000h
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WRMSR
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;Writing DIAGCTL Register to enable the stall action and to let set5m watch the upper GeodeLink diag bits.
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mov ecx, MSR_GLCP + 005fh
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xor edx, edx
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mov eax, 80004000h
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WRMSR
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bug2900exit:
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popad
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ret
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CPUbugIAENG2900 ENDP
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#endif
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/* Writing DIAGCTL Register to enable the stall action and to
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let set5m watch the upper GeodeLink diag bits. */
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msr.hi = 0;
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msr.lo = 0x80004000;
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wrmsr(MSR_GLCP + 0x005f, msr);
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}
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}
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void bug118253(void)
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@ -95,7 +95,7 @@ struct msrinit GeodeLinkPriorityTable [] = {
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{DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority.*/
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{VG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0720}}, /* VG Primary and Secondary Priority.*/
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{GP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0010}}, /* Graphics Priority.*/
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{GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0017}}, /* GLPCI Priority + PID*/
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{GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0027}}, /* GLPCI Priority + PID*/
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{GLCP_GLD_MSR_CONF, {.hi=0x00,.lo=0x0001}}, /* GLCP Priority + PID*/
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{VIP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0622}}, /* VIP PID*/
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{AES_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0013}}, /* AES PID*/
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