riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handler

Change-Id: Ic42d8490cc02a3907e2989435aab786f7c0f39c9
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15287
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/arch/riscv/bootblock.S

@@ -38,10 +38,10 @@ _start:
   sd t0, 0(t1)
 
   la t0, exception_handler
-  csrw stvec, t0
+  csrw mtvec, t0
 
   # clear any pending interrupts
-  csrwi sip, 0
+  csrwi mip, 0
 
   # set up the mstatus register for VM
   call mstatus_init