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riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handler 

Change-Id: Ic42d8490cc02a3907e2989435aab786f7c0f39c9
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15287
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Jonathan Neuschäfer 2016-06-21 19:37:03 +02:00 committed by Martin Roth
parent fefc77afd0
commit 9d0cce2087
1 changed files with 2 additions and 2 deletions
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4
src/arch/riscv/bootblock.S
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@ -38,10 +38,10 @@ _start:
sd t0, 0(t1) sd t0, 0(t1)
la t0, exception_handler la t0, exception_handler
csrw stvec, t0 csrw mtvec, t0
# clear any pending interrupts # clear any pending interrupts
csrwi sip, 0 csrwi mip, 0
# set up the mstatus register for VM # set up the mstatus register for VM
call mstatus_init call mstatus_init