GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/brya/var/vell: Remove Rcomp settings 

This patch removes Rcomp settings. In MRC design, it checks if the
Rcomp settings from the board is 0 or null, if so, it uses the
recommended Rcomp values. Otherwise, it uses the Rcomp settings passed
from the UPD. From the change history of MRC, we're chasing a moving
target. This RCOMP setting in coreboot is an old setting while the
Rcomp settins in MRC are optimized settings. Moving forward, if there
is a new stepping, it might be changed again which increases the
maintenance effort in coreboot. IMHO, we should let MRC to set the
optimized RCOMP values for the design.

BUG=b:219378758
TEST=emerge-byra coreboot chromeos-bootimage and boots up with QS and
     PRQ CPUs. Checks with MRC log and ensure the RCOMP settings are
     filled properly by MRC.

Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: I8547e187b74f9b2cee57ddad2883d60c05d0b9fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Gaggery Tsai 2022-02-17 11:37:59 -08:00 committed by Felix Held
parent 7a7a533725
commit 9d0fc3f396
1 changed files with 1 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/google/brya/variants/vell/memory.c
View File

@ -8,13 +8,7 @@
static const struct mb_cfg baseboard_memcfg = { static const struct mb_cfg baseboard_memcfg = {
.type = MEM_TYPE_LP5X, .type = MEM_TYPE_LP5X,
.rcomp = { /* Leave Rcomp unspecified to use the FSP optimized defaults */
/* Baseboard uses only 100ohm Rcomp resistors */
.resistor = 100,
/* Baseboard Rcomp target values */
.targets = { 40, 36, 35, 35, 35 },
},
/* DQ byte map */ /* DQ byte map */
.lpx_dq_map = { .lpx_dq_map = {