intel/amenia: Write protect GPIO relative to bank offset

Update the write protect GPIO reported in ACPI to GPIO_75.
Also update the controller ID to "INT3452:01" which will
point at the goldmont device and includes write protect GPIO.

BUG=none
BRANCH=none
TEST=verify crossystem output for wpsw_cur.

Change-Id: Id6b172e289976072836746c1814e0300544a06cb
Signed-off-by: sselvar2 <susendra.selvaraj@intel.com>
Reviewed-on: https://coreboot.intel.com/7771
Reviewed-by: Sparry, Icarus W <icarus.w.sparry@intel.com>
Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15496
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/mainboard/intel/amenia/acpi/chromeos.asl

@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/gpio_defs.h>
+
+Name (OIPG, Package () {
+	/* No physical recovery GPIO. */
+	Package () { 0x0001, 0, 0xFFFFFFFF, "INT3452:01" },
+	/* Firmware write protect GPIO. */
+	Package () { 0x0003, 1, PAD_NW(GPIO_75), "INT3452:01" },
+})

src/mainboard/intel/amenia/dsdt.asl

@@ -38,6 +38,12 @@ DefinitionBlock(
 			#include <soc/intel/apollolake/acpi/pch_hda.asl>
 		}
 	}
+
+	#if IS_ENABLED(CONFIG_CHROMEOS)
+	#include "acpi/chromeos.asl"
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+	#endif
+
 	/* Mainboard Specific devices */
 	#include "acpi/mainboard.asl"