soc/mediatek: move i2c function to common folder
Move mtk_i2c_max_step_cnt, mtk_i2c_check_ac_timing, mtk_i2c_speed_init and mtk_i2c_calculate_speed to common folder to share with MT8186. TEST=test on tomato ok TEST=emerge-asurada coreboot BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I4a702741c763bf9261cea90d0d71c08b6e28c261 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Rex-BC Chen
Hung-Te Lin
parent
e2cc773f71
commit
9d321588d0
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@ -8,6 +8,7 @@
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#include <symbols.h>
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#include <device/mmio.h>
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#include <soc/i2c.h>
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#include <soc/i2c_common.h>
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#include <device/i2c_simple.h>
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const struct i2c_spec_values standard_mode_spec = {
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@ -31,7 +32,15 @@ const struct i2c_spec_values fast_mode_plus_spec = {
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.min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER,
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};
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__weak void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs) { /* do nothing */ }
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__weak void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs)
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{
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/* do nothing */
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}
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__weak void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl)
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{
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/* do nothing */
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}
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const struct i2c_spec_values *mtk_i2c_get_spec(uint32_t speed)
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{
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@ -281,6 +290,14 @@ static bool mtk_i2c_should_combine(struct i2c_msg *seg, int left_count)
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seg[0].slave == seg[1].slave);
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}
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static int mtk_i2c_max_step_cnt(uint32_t target_speed)
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{
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if (target_speed > I2C_SPEED_FAST_PLUS)
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return MAX_HS_STEP_CNT_DIV;
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else
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return MAX_STEP_CNT_DIV;
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}
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int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments,
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int seg_count)
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{
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@ -307,3 +324,230 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments,
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return ret;
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}
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/*
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* Check and calculate i2c ac-timing.
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*
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* Hardware design:
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* sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src
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* xxx_cnt_div = spec->min_xxx_ns / sample_ns
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*
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* The calculation of sample_ns is rounded down;
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* otherwise xxx_cnt_div would be greater than the smallest spec.
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* The sda_timing is chosen as the middle value between
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* the largest and smallest.
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*/
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int mtk_i2c_check_ac_timing(uint8_t bus, uint32_t clk_src,
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uint32_t check_speed,
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uint32_t step_cnt,
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uint32_t sample_cnt)
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{
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const struct i2c_spec_values *spec;
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uint32_t su_sta_cnt, low_cnt, high_cnt, max_step_cnt;
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uint32_t sda_max, sda_min, clk_ns, max_sta_cnt = 0x100;
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uint32_t sample_ns = ((uint64_t)NSECS_PER_SEC * (sample_cnt + 1)) / clk_src;
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struct mtk_i2c_ac_timing *ac_timing;
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spec = mtk_i2c_get_spec(check_speed);
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clk_ns = NSECS_PER_SEC / clk_src;
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su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns);
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if (su_sta_cnt > max_sta_cnt)
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return -1;
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low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns);
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max_step_cnt = mtk_i2c_max_step_cnt(check_speed);
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if (2 * step_cnt > low_cnt && low_cnt < max_step_cnt) {
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if (low_cnt > step_cnt) {
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high_cnt = 2 * step_cnt - low_cnt;
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} else {
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high_cnt = step_cnt;
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low_cnt = step_cnt;
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}
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} else {
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return -2;
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}
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sda_max = spec->max_hd_dat_ns / sample_ns;
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if (sda_max > low_cnt)
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sda_max = 0;
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sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns);
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if (sda_min < low_cnt)
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sda_min = 0;
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if (sda_min > sda_max)
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return -3;
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ac_timing = &mtk_i2c_bus_controller[bus].ac_timing;
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if (check_speed > I2C_SPEED_FAST_PLUS) {
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ac_timing->hs = I2C_TIME_DEFAULT_VALUE | (sample_cnt << 12) | (high_cnt << 8);
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ac_timing->ltiming &= ~GENMASK(15, 9);
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ac_timing->ltiming |= (sample_cnt << 12) | (low_cnt << 9);
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ac_timing->ext &= ~GENMASK(7, 1);
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ac_timing->ext |= (su_sta_cnt << 1) | (1 << 0);
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} else {
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ac_timing->htiming = (sample_cnt << 8) | (high_cnt);
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ac_timing->ltiming = (sample_cnt << 6) | (low_cnt);
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ac_timing->ext = (su_sta_cnt << 8) | (1 << 0);
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}
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return 0;
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}
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/*
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* Calculate i2c port speed.
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*
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* Hardware design:
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* i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
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* clock_div: fixed in hardware, but may be various in different SoCs
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*
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* To calculate sample_cnt and step_cnt, we pick the highest bus frequency
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* that is still no larger than i2c->speed_hz.
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*/
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int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src,
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uint32_t target_speed,
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uint32_t *timing_step_cnt,
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uint32_t *timing_sample_cnt)
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{
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uint32_t step_cnt;
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uint32_t sample_cnt;
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uint32_t max_step_cnt;
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uint32_t base_sample_cnt = MAX_SAMPLE_CNT_DIV;
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uint32_t base_step_cnt;
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uint32_t opt_div;
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uint32_t best_mul;
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uint32_t cnt_mul;
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uint32_t clk_div = mtk_i2c_bus_controller[bus].ac_timing.inter_clk_div;
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int32_t clock_div_constraint = 0;
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int success = 0;
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if (target_speed > I2C_SPEED_HIGH)
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target_speed = I2C_SPEED_HIGH;
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max_step_cnt = mtk_i2c_max_step_cnt(target_speed);
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base_step_cnt = max_step_cnt;
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/* Find the best combination */
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opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
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best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
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/* Search for the best pair (sample_cnt, step_cnt) with
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* 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
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* 0 < step_cnt < max_step_cnt
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* sample_cnt * step_cnt >= opt_div
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* optimizing for sample_cnt * step_cnt being minimal
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*/
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for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
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if (sample_cnt == 1) {
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if (clk_div != 0)
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clock_div_constraint = 1;
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else
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clock_div_constraint = 0;
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} else {
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if (clk_div > 1)
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clock_div_constraint = 1;
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else if (clk_div == 0)
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clock_div_constraint = -1;
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else
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clock_div_constraint = 0;
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}
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step_cnt = DIV_ROUND_UP(opt_div + clock_div_constraint, sample_cnt);
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if (step_cnt > max_step_cnt)
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continue;
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cnt_mul = step_cnt * sample_cnt;
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if (cnt_mul >= best_mul)
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continue;
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if (mtk_i2c_check_ac_timing(bus, clk_src,
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target_speed, step_cnt - 1,
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sample_cnt - 1))
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continue;
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success = 1;
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best_mul = cnt_mul;
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base_sample_cnt = sample_cnt;
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base_step_cnt = step_cnt;
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if (best_mul == opt_div + clock_div_constraint)
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break;
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}
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if (!success)
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return -1;
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sample_cnt = base_sample_cnt;
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step_cnt = base_step_cnt;
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if (clk_src / (2 * (sample_cnt * step_cnt - clock_div_constraint)) >
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target_speed)
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return -1;
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*timing_step_cnt = step_cnt - 1;
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*timing_sample_cnt = sample_cnt - 1;
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return 0;
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}
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void mtk_i2c_speed_init(uint8_t bus, uint32_t speed)
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{
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uint32_t max_clk_div = MAX_CLOCK_DIV;
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uint32_t clk_src, clk_div, step_cnt, sample_cnt;
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uint32_t l_step_cnt, l_sample_cnt;
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uint32_t timing_reg_value, ltiming_reg_value;
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struct mtk_i2c *bus_ctrl;
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if (bus >= I2C_BUS_NUMBER) {
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printk(BIOS_ERR, "%s, error bus num:%d\n", __func__, bus);
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return;
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}
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bus_ctrl = &mtk_i2c_bus_controller[bus];
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for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
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clk_src = I2C_CLK_HZ / clk_div;
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bus_ctrl->ac_timing.inter_clk_div = clk_div - 1;
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if (speed > I2C_SPEED_FAST_PLUS) {
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/* Set master code speed register */
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if (mtk_i2c_calculate_speed(bus, clk_src, I2C_SPEED_FAST,
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&l_step_cnt, &l_sample_cnt))
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continue;
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timing_reg_value = (l_sample_cnt << 8) | l_step_cnt;
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/* Set the high speed mode register */
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if (mtk_i2c_calculate_speed(bus, clk_src, speed,
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&step_cnt, &sample_cnt))
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continue;
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ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt |
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(sample_cnt << 12) | (step_cnt << 9);
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bus_ctrl->ac_timing.inter_clk_div = (clk_div - 1) << 8 | (clk_div - 1);
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} else {
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if (mtk_i2c_calculate_speed(bus, clk_src, speed,
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&l_step_cnt, &l_sample_cnt))
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continue;
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timing_reg_value = (l_sample_cnt << 8) | l_step_cnt;
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/* Disable the high speed transaction */
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bus_ctrl->ac_timing.hs = I2C_TIME_CLR_VALUE;
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ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt;
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}
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break;
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}
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if (clk_div > max_clk_div) {
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printk(BIOS_ERR, "%s, cannot support %d hz on i2c-%d\n", __func__, speed, bus);
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return;
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}
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/* Init i2c bus timing register. */
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mtk_i2c_config_timing(bus_ctrl->i2c_regs, bus_ctrl);
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}
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@ -143,4 +143,15 @@ extern struct mtk_i2c mtk_i2c_bus_controller[];
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const struct i2c_spec_values *mtk_i2c_get_spec(uint32_t speed);
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void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs);
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int mtk_i2c_check_ac_timing(uint8_t bus, uint32_t clk_src,
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uint32_t check_speed,
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uint32_t step_cnt,
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uint32_t sample_cnt);
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int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src,
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uint32_t target_speed,
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uint32_t *timing_step_cnt,
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uint32_t *timing_sample_cnt);
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void mtk_i2c_speed_init(uint8_t bus, uint32_t speed);
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void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl);
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#endif
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@ -6,9 +6,6 @@
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#include <device/mmio.h>
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#include <soc/addressmap.h>
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#include <soc/i2c.h>
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#include <soc/pll.h>
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#define I2C_CLK_HZ (AXI_HZ / 16)
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struct mtk_i2c mtk_i2c_bus_controller[7] = {
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/* i2c0 setting */
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@ -52,6 +49,9 @@ struct mtk_i2c mtk_i2c_bus_controller[7] = {
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}
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};
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_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER,
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"Wrong size of mtk_i2c_bus_controller");
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#define I2CTAG "[I2C][PL] "
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#if CONFIG(DEBUG_I2C)
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@ -4,6 +4,7 @@
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#define SOC_MEDIATEK_MT8173_I2C_H
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#include <soc/i2c_common.h>
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#include <soc/pll.h>
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/* I2C Register */
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struct mt_i2c_regs {
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@ -35,6 +36,10 @@ struct mt_i2c_regs {
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uint32_t transfer_aux_len;
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};
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#define I2C_CLK_HZ (AXI_HZ / 16)
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#define I2C_BUS_NUMBER 7
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#define MAX_CLOCK_DIV 32
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check_member(mt_i2c_regs, debug_stat, 0x64);
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void mtk_i2c_bus_init(uint8_t bus);
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@ -2,12 +2,9 @@
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#include <assert.h>
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#include <device/mmio.h>
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#include <soc/pll.h>
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#include <soc/i2c.h>
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#include <soc/gpio.h>
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#define I2C_CLK_HZ (UNIVPLL_HZ / 20)
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struct mtk_i2c mtk_i2c_bus_controller[] = {
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/* i2c0 setting */
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{
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@ -52,7 +49,8 @@ struct mtk_i2c mtk_i2c_bus_controller[] = {
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},
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};
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#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller)
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_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER,
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"Wrong size of mtk_i2c_bus_controller");
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struct pad_func {
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gpio_t gpio;
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@ -103,7 +101,7 @@ static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
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}
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}
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static void mtk_i2c_speed_init(uint8_t bus)
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static void mtk_i2c_speed_init_soc(uint8_t bus)
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{
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uint8_t step_div;
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const uint8_t clock_div = 5;
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@ -132,7 +130,7 @@ static void mtk_i2c_speed_init(uint8_t bus)
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void mtk_i2c_bus_init(uint8_t bus)
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{
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mtk_i2c_speed_init(bus);
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mtk_i2c_speed_init_soc(bus);
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mtk_i2c_set_gpio_pinmux(bus);
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}
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@ -4,6 +4,7 @@
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#define SOC_MEDIATEK_MT8183_I2C_H
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#include <soc/i2c_common.h>
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#include <soc/pll.h>
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/* I2C Register */
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struct mt_i2c_regs {
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@ -39,6 +40,10 @@ struct mt_i2c_regs {
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uint32_t rollback;
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};
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#define I2C_CLK_HZ (UNIVPLL_HZ / 20)
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#define I2C_BUS_NUMBER 7
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#define MAX_CLOCK_DIV 32
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check_member(mt_i2c_regs, multi_dma, 0xf8c);
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void mtk_i2c_bus_init(uint8_t bus);
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@ -2,11 +2,9 @@
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#include <assert.h>
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#include <device/mmio.h>
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#include <soc/pll.h>
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#include <soc/i2c.h>
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#include <soc/gpio.h>
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#define I2C_CLK_HZ (UNIVPLL_HZ / 20)
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#define I2C_FULL_DUTY 100
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#define I2C_HALF_DUTY 50
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#define I2C_ADJUSTED_DUTY 45
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@ -64,7 +62,8 @@ struct mtk_i2c mtk_i2c_bus_controller[] = {
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},
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};
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#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller)
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_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER,
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"Wrong size of mtk_i2c_bus_controller");
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struct pad_func {
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gpio_t gpio;
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@ -127,7 +126,7 @@ static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
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}
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}
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|
||||
static void mtk_i2c_speed_init(uint8_t bus)
|
||||
static void mtk_i2c_speed_init_soc(uint8_t bus)
|
||||
{
|
||||
uint8_t step_div;
|
||||
const uint8_t clock_div = 5;
|
||||
|
|
@ -178,7 +177,7 @@ static void mtk_i2c_speed_init(uint8_t bus)
|
|||
|
||||
void mtk_i2c_bus_init(uint8_t bus)
|
||||
{
|
||||
mtk_i2c_speed_init(bus);
|
||||
mtk_i2c_speed_init_soc(bus);
|
||||
mtk_i2c_set_gpio_pinmux(bus);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
#define SOC_MEDIATEK_MT8192_I2C_H
|
||||
|
||||
#include <soc/i2c_common.h>
|
||||
#include <soc/pll.h>
|
||||
|
||||
/* I2C Register */
|
||||
struct mt_i2c_regs {
|
||||
|
|
@ -39,6 +40,10 @@ struct mt_i2c_regs {
|
|||
uint32_t rollback;
|
||||
};
|
||||
|
||||
#define I2C_BUS_NUMBER 10
|
||||
#define MAX_CLOCK_DIV 32
|
||||
#define I2C_CLK_HZ (UNIVPLL_HZ / 20)
|
||||
|
||||
check_member(mt_i2c_regs, multi_dma, 0xf8c);
|
||||
|
||||
void mtk_i2c_bus_init(uint8_t bus);
|
||||
|
|
|
|||
|
|
@ -4,13 +4,10 @@
|
|||
#include <console/console.h>
|
||||
#include <device/mmio.h>
|
||||
#include <device/i2c_simple.h>
|
||||
#include <soc/pll.h>
|
||||
#include <soc/i2c.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <timer.h>
|
||||
|
||||
#define I2C_CLK_HZ (UNIVPLL_HZ / 20)
|
||||
|
||||
struct mtk_i2c mtk_i2c_bus_controller[] = {
|
||||
[0] = {
|
||||
.i2c_regs = (void *)(I2C_BASE),
|
||||
|
|
@ -54,7 +51,8 @@ struct mtk_i2c mtk_i2c_bus_controller[] = {
|
|||
},
|
||||
};
|
||||
|
||||
#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller)
|
||||
_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER,
|
||||
"Wrong size of mtk_i2c_bus_controller");
|
||||
|
||||
struct pad_func {
|
||||
gpio_t gpio;
|
||||
|
|
@ -111,245 +109,6 @@ static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
|
|||
}
|
||||
}
|
||||
|
||||
static int mtk_i2c_max_step_cnt(uint32_t target_speed)
|
||||
{
|
||||
if (target_speed > I2C_SPEED_FAST_PLUS)
|
||||
return MAX_HS_STEP_CNT_DIV;
|
||||
else
|
||||
return MAX_STEP_CNT_DIV;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check and calculate i2c ac-timing.
|
||||
*
|
||||
* Hardware design:
|
||||
* sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src
|
||||
* xxx_cnt_div = spec->min_xxx_ns / sample_ns
|
||||
*
|
||||
* The calculation of sample_ns is rounded down;
|
||||
* otherwise xxx_cnt_div would be greater than the smallest spec.
|
||||
* The sda_timing is chosen as the middle value between
|
||||
* the largest and smallest.
|
||||
*/
|
||||
static int mtk_i2c_check_ac_timing(uint8_t bus, uint32_t clk_src,
|
||||
uint32_t check_speed,
|
||||
uint32_t step_cnt,
|
||||
uint32_t sample_cnt)
|
||||
{
|
||||
const struct i2c_spec_values *spec;
|
||||
uint32_t su_sta_cnt, low_cnt, high_cnt, max_step_cnt;
|
||||
uint32_t sda_max, sda_min, clk_ns, max_sta_cnt = 0x100;
|
||||
uint32_t sample_ns = ((uint64_t)NSECS_PER_SEC * (sample_cnt + 1)) / clk_src;
|
||||
struct mtk_i2c_ac_timing *ac_timing;
|
||||
|
||||
spec = mtk_i2c_get_spec(check_speed);
|
||||
|
||||
clk_ns = NSECS_PER_SEC / clk_src;
|
||||
|
||||
su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns);
|
||||
if (su_sta_cnt > max_sta_cnt)
|
||||
return -1;
|
||||
|
||||
low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns);
|
||||
max_step_cnt = mtk_i2c_max_step_cnt(check_speed);
|
||||
if (2 * step_cnt > low_cnt && low_cnt < max_step_cnt) {
|
||||
if (low_cnt > step_cnt) {
|
||||
high_cnt = 2 * step_cnt - low_cnt;
|
||||
} else {
|
||||
high_cnt = step_cnt;
|
||||
low_cnt = step_cnt;
|
||||
}
|
||||
} else {
|
||||
return -2;
|
||||
}
|
||||
|
||||
sda_max = spec->max_hd_dat_ns / sample_ns;
|
||||
if (sda_max > low_cnt)
|
||||
sda_max = 0;
|
||||
|
||||
sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns);
|
||||
if (sda_min < low_cnt)
|
||||
sda_min = 0;
|
||||
|
||||
if (sda_min > sda_max)
|
||||
return -3;
|
||||
|
||||
ac_timing = &mtk_i2c_bus_controller[bus].ac_timing;
|
||||
if (check_speed > I2C_SPEED_FAST_PLUS) {
|
||||
ac_timing->hs = I2C_TIME_DEFAULT_VALUE | (sample_cnt << 12) | (high_cnt << 8);
|
||||
ac_timing->ltiming &= ~GENMASK(15, 9);
|
||||
ac_timing->ltiming |= (sample_cnt << 12) | (low_cnt << 9);
|
||||
ac_timing->ext &= ~GENMASK(7, 1);
|
||||
ac_timing->ext |= (su_sta_cnt << 1) | (1 << 0);
|
||||
} else {
|
||||
ac_timing->htiming = (sample_cnt << 8) | (high_cnt);
|
||||
ac_timing->ltiming = (sample_cnt << 6) | (low_cnt);
|
||||
ac_timing->ext = (su_sta_cnt << 8) | (1 << 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Calculate i2c port speed.
|
||||
*
|
||||
* Hardware design:
|
||||
* i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
|
||||
* clock_div: fixed in hardware, but may be various in different SoCs
|
||||
*
|
||||
* To calculate sample_cnt and step_cnt, we pick the highest bus frequency
|
||||
* that is still no larger than i2c->speed_hz.
|
||||
*/
|
||||
static int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src,
|
||||
uint32_t target_speed,
|
||||
uint32_t *timing_step_cnt,
|
||||
uint32_t *timing_sample_cnt)
|
||||
{
|
||||
uint32_t step_cnt;
|
||||
uint32_t sample_cnt;
|
||||
uint32_t max_step_cnt;
|
||||
uint32_t base_sample_cnt = MAX_SAMPLE_CNT_DIV;
|
||||
uint32_t base_step_cnt;
|
||||
uint32_t opt_div;
|
||||
uint32_t best_mul;
|
||||
uint32_t cnt_mul;
|
||||
uint32_t clk_div = mtk_i2c_bus_controller[bus].ac_timing.inter_clk_div;
|
||||
int32_t clock_div_constraint = 0;
|
||||
int success = 0;
|
||||
|
||||
if (target_speed > I2C_SPEED_HIGH)
|
||||
target_speed = I2C_SPEED_HIGH;
|
||||
|
||||
max_step_cnt = mtk_i2c_max_step_cnt(target_speed);
|
||||
base_step_cnt = max_step_cnt;
|
||||
|
||||
/* Find the best combination */
|
||||
opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
|
||||
best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
|
||||
|
||||
/* Search for the best pair (sample_cnt, step_cnt) with
|
||||
* 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
|
||||
* 0 < step_cnt < max_step_cnt
|
||||
* sample_cnt * step_cnt >= opt_div
|
||||
* optimizing for sample_cnt * step_cnt being minimal
|
||||
*/
|
||||
for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
|
||||
if (sample_cnt == 1) {
|
||||
if (clk_div != 0)
|
||||
clock_div_constraint = 1;
|
||||
else
|
||||
clock_div_constraint = 0;
|
||||
} else {
|
||||
if (clk_div > 1)
|
||||
clock_div_constraint = 1;
|
||||
else if (clk_div == 0)
|
||||
clock_div_constraint = -1;
|
||||
else
|
||||
clock_div_constraint = 0;
|
||||
}
|
||||
|
||||
step_cnt = DIV_ROUND_UP(opt_div + clock_div_constraint, sample_cnt);
|
||||
if (step_cnt > max_step_cnt)
|
||||
continue;
|
||||
|
||||
cnt_mul = step_cnt * sample_cnt;
|
||||
if (cnt_mul >= best_mul)
|
||||
continue;
|
||||
|
||||
if (mtk_i2c_check_ac_timing(bus, clk_src,
|
||||
target_speed, step_cnt - 1,
|
||||
sample_cnt - 1))
|
||||
continue;
|
||||
|
||||
success = 1;
|
||||
best_mul = cnt_mul;
|
||||
base_sample_cnt = sample_cnt;
|
||||
base_step_cnt = step_cnt;
|
||||
if (best_mul == opt_div + clock_div_constraint)
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
if (!success)
|
||||
return -1;
|
||||
|
||||
sample_cnt = base_sample_cnt;
|
||||
step_cnt = base_step_cnt;
|
||||
|
||||
if (clk_src / (2 * (sample_cnt * step_cnt - clock_div_constraint)) >
|
||||
target_speed)
|
||||
return -1;
|
||||
|
||||
*timing_step_cnt = step_cnt - 1;
|
||||
*timing_sample_cnt = sample_cnt - 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mtk_i2c_speed_init(uint8_t bus, uint32_t speed)
|
||||
{
|
||||
uint32_t max_clk_div = MAX_CLOCK_DIV;
|
||||
uint32_t clk_src, clk_div, step_cnt, sample_cnt;
|
||||
uint32_t l_step_cnt, l_sample_cnt;
|
||||
uint32_t timing_reg_value, ltiming_reg_value;
|
||||
struct mtk_i2c *bus_ctrl;
|
||||
|
||||
if (bus >= I2C_BUS_NUMBER) {
|
||||
printk(BIOS_ERR, "%s, error bus num:%d\n", __func__, bus);
|
||||
return;
|
||||
}
|
||||
|
||||
bus_ctrl = &mtk_i2c_bus_controller[bus];
|
||||
|
||||
for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
|
||||
clk_src = I2C_CLK_HZ / clk_div;
|
||||
bus_ctrl->ac_timing.inter_clk_div = clk_div - 1;
|
||||
|
||||
if (speed > I2C_SPEED_FAST_PLUS) {
|
||||
/* Set master code speed register */
|
||||
if (mtk_i2c_calculate_speed(bus, clk_src, I2C_SPEED_FAST,
|
||||
&l_step_cnt, &l_sample_cnt))
|
||||
continue;
|
||||
|
||||
timing_reg_value = (l_sample_cnt << 8) | l_step_cnt;
|
||||
|
||||
/* Set the high speed mode register */
|
||||
if (mtk_i2c_calculate_speed(bus, clk_src, speed,
|
||||
&step_cnt, &sample_cnt))
|
||||
continue;
|
||||
|
||||
ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt |
|
||||
(sample_cnt << 12) | (step_cnt << 9);
|
||||
bus_ctrl->ac_timing.inter_clk_div = (clk_div - 1) << 8 | (clk_div - 1);
|
||||
} else {
|
||||
if (mtk_i2c_calculate_speed(bus, clk_src, speed,
|
||||
&l_step_cnt, &l_sample_cnt))
|
||||
continue;
|
||||
|
||||
timing_reg_value = (l_sample_cnt << 8) | l_step_cnt;
|
||||
|
||||
/* Disable the high speed transaction */
|
||||
bus_ctrl->ac_timing.hs = I2C_TIME_CLR_VALUE;
|
||||
|
||||
ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt;
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
if (clk_div > max_clk_div) {
|
||||
printk(BIOS_ERR, "%s, cannot support %d hz on i2c-%d\n", __func__, speed, bus);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Init i2c bus timing register */
|
||||
write32(&bus_ctrl->i2c_regs->clock_div, bus_ctrl->ac_timing.inter_clk_div);
|
||||
write32(&bus_ctrl->i2c_regs->timing, bus_ctrl->ac_timing.htiming);
|
||||
write32(&bus_ctrl->i2c_regs->ltiming, bus_ctrl->ac_timing.ltiming);
|
||||
write32(&bus_ctrl->i2c_regs->hs, bus_ctrl->ac_timing.hs);
|
||||
write32(&bus_ctrl->i2c_regs->ext_conf, bus_ctrl->ac_timing.ext);
|
||||
}
|
||||
|
||||
void mtk_i2c_bus_init(uint8_t bus, uint32_t speed)
|
||||
{
|
||||
mtk_i2c_speed_init(bus, speed);
|
||||
|
|
@ -362,3 +121,12 @@ void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs)
|
|||
read32(®s->ltiming),
|
||||
read32(®s->clock_div));
|
||||
}
|
||||
|
||||
void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl)
|
||||
{
|
||||
write32(®s->clock_div, bus_ctrl->ac_timing.inter_clk_div);
|
||||
write32(®s->timing, bus_ctrl->ac_timing.htiming);
|
||||
write32(®s->ltiming, bus_ctrl->ac_timing.ltiming);
|
||||
write32(®s->hs, bus_ctrl->ac_timing.hs);
|
||||
write32(®s->ext_conf, bus_ctrl->ac_timing.ext);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
#define SOC_MEDIATEK_MT8195_I2C_H
|
||||
|
||||
#include <soc/i2c_common.h>
|
||||
#include <soc/pll.h>
|
||||
|
||||
/* I2C Register */
|
||||
struct mt_i2c_regs {
|
||||
|
|
@ -52,7 +53,10 @@ enum {
|
|||
I2C7,
|
||||
};
|
||||
|
||||
#define I2C_BUS_NUMBER 8
|
||||
#define MAX_CLOCK_DIV 32
|
||||
#define I2C_CLK_HZ (UNIVPLL_HZ / 20)
|
||||
|
||||
check_member(mt_i2c_regs, multi_dma, 0xf8c);
|
||||
|
||||
void mtk_i2c_bus_init(uint8_t bus, uint32_t speed);
|
||||
|
|
|
|||
Loading…
Reference in New Issue