bd82x6x: Support power-on-after-power-fail better
Changing CMOS value for power-on-after-power-fail was only honored after reboot, which is counter intuitive (set from "enable" to "disable", power-off, replug device -> device turns on; and similar cases). Modelled after http://review.coreboot.org/#/c/444 Change-Id: I2b8461dff1ae085c1ea4b4926084268b4da90321 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1323 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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@ -362,16 +362,16 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
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outl(0, pmbase + GPE0_EN);
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outl(0, pmbase + GPE0_EN);
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/* Should we keep the power state after a power loss?
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/* Always set the flag in case CMOS was changed on runtime. For
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* In case the setting is "ON" or "OFF" we don't have
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* "KEEP", switch to "OFF" - KEEP is software emulated
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* to do anything. But if it's "KEEP" we have to switch
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* to "OFF" before entering S5.
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*/
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*/
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if (s5pwr == MAINBOARD_POWER_KEEP) {
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reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
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reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
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if (s5pwr == MAINBOARD_POWER_ON) {
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reg8 &= ~1;
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} else {
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reg8 |= 1;
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reg8 |= 1;
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pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
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}
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}
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pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
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/* also iterates over all bridges on bus 0 */
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/* also iterates over all bridges on bus 0 */
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busmaster_disable_on_bus(0);
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busmaster_disable_on_bus(0);
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