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bd82x6x: Support power-on-after-power-fail better 

Changing CMOS value for power-on-after-power-fail was only honored
after reboot, which is counter intuitive (set from "enable" to
"disable",
power-off, replug device -> device turns on; and similar cases).

Modelled after http://review.coreboot.org/#/c/444

Change-Id: I2b8461dff1ae085c1ea4b4926084268b4da90321
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1323
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Stefan Reinauer 2012-06-28 12:18:41 -07:00 committed by Patrick Georgi
parent df0c822239
commit 9d3e832c72
1 changed files with 7 additions and 7 deletions
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12
src/southbridge/intel/bd82x6x/smihandler.c
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@ -362,16 +362,16 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
outl(0, pmbase + GPE0_EN);
/* Should we keep the power state after a power loss?
* In case the setting is "ON" or "OFF" we don't have
* to do anything. But if it's "KEEP" we have to switch
* to "OFF" before entering S5.
/* Always set the flag in case CMOS was changed on runtime. For
* "KEEP", switch to "OFF" - KEEP is software emulated
*/
if (s5pwr == MAINBOARD_POWER_KEEP) {
reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
if (s5pwr == MAINBOARD_POWER_ON) {
reg8 &= ~1;
} else {
reg8 |= 1;
pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
}
pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);