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mb/intel/tglrvp: Enable RTD3 for WWAN 

Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root
Port 4 and provide the reset GPIO / src clk pin.

BUG=none
TEST=Boot to OS, verify the link is in L2 state during S0ix.

Change-Id: I669e02bd02e3af878648a6f3cf4fbb4d06c9857f
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This commit is contained in:
Bora Guvendik 2021-03-01 14:32:16 -08:00 committed by Patrick Georgi
parent 011e1b3fbc
commit 9d4d2d014c
2 changed files with 14 additions and 2 deletions
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8
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -288,7 +288,13 @@ chip soc/intel/tigerlake
device pci 1c.0 off end # RP1 0xA0B8
device pci 1c.1 off end # RP2 0xA0B9
device pci 1c.2 on end # RP3 0xA0BA
device pci 1c.3 on end # RP4 0xA0BB
device pci 1c.3 on
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)"
register "srcclk_pin" = "2"
device generic 0 on end
end
end # RP4 0xA0BB
device pci 1c.4 off end # RP5 0xA0BC
device pci 1c.5 off end # RP6 0xA0BD
device pci 1c.6 off end # RP7 0xA0BE

8
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -292,7 +292,13 @@ chip soc/intel/tigerlake
device pci 1c.0 off end # RP1 0xA0B8
device pci 1c.1 off end # RP2 0xA0B9
device pci 1c.2 on end # RP3 0xA0BA
device pci 1c.3 on end # RP4 0xA0BB
device pci 1c.3 on
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)"
register "srcclk_pin" = "2"
device generic 0 on end
end
end # RP4 0xA0BB
device pci 1c.4 off end # RP5 0xA0BC
device pci 1c.5 off end # RP6 0xA0BD
device pci 1c.6 off end # RP7 0xA0BE