diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index f05f15749e..1d59f1a982 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -11,6 +11,13 @@ config EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
 	  not defined, the memmap data is instead accessed on 900h-9ffh via
 	  the LPC bus.
 
+config EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER
+	depends on EC_GOOGLE_CHROMEEC
+	def_bool n
+	help
+	  Expose methods for enabling and disabling port power on individual USB
+	  ports through the EC.
+
 config EC_GOOGLE_CHROMEEC_BOARDID
 	depends on EC_GOOGLE_CHROMEEC
 	def_bool n
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
index ac4ceb16c5..dc0f60903e 100644
--- a/src/ec/google/chromeec/acpi/ec.asl
+++ b/src/ec/google/chromeec/acpi/ec.asl
@@ -91,6 +91,7 @@ Device (EC0)
 		Offset (0x0e),
 		Offset (0x12),
 		BTID, 8,	// Battery index that host wants to read
+		USPP, 8,	// USB Port Power
 }
 
 #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP)
@@ -512,6 +513,26 @@ Device (EC0)
 		Return (^TBMD)
 	}
 
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER)
+	/*
+	 * Enable USB Port Power
+	 *   Arg0 = USB port ID
+	 */
+	Method (UPPS, 1, Serialized)
+	{
+		Or (USPP, ShiftLeft (1, Arg0), USPP)
+	}
+
+	/*
+	 * Disable USB Port Power
+	 *   Arg0 = USB port ID
+	 */
+	Method (UPPC, 1, Serialized)
+	{
+		And (USPP, Not (ShiftLeft (1, Arg0)), USPP)
+	}
+#endif
+
 	#include "ac.asl"
 	#include "battery.asl"
 	#include "cros_ec.asl"