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soc/mediatek: Move some SPM functions to common 

Some functions are the same in spm.c for MT8192, MT8195, MT8186 and
MT8188, so we move them to common/spm.c.

TEST=build pass.
BUG=b:236331724

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I29ddefc47d8bd156fa1ca0cedd4deaed676ae7e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Bo-Chen Chen 2022-08-29 19:09:38 +08:00 committed by Felix Held
parent dcdbda5c93
commit 9d638a9516
8 changed files with 232 additions and 552 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/soc/mediatek/common/include/soc/spm_common.h
View File

@ -5,5 +5,27 @@
#include <soc/mcu_common.h> #include <soc/mcu_common.h>
void spm_parse_firmware(struct mtk_mcu *mcu); #define SPM_SYSTEM_BASE_OFFSET 0x40000000
struct pcm_desc {
u32 pmem_words;
u32 total_words;
u32 pmem_start;
u32 dmem_start;
};
struct dyna_load_pcm {
u8 *buf; /* binary array */
struct pcm_desc desc;
};
const struct pwr_ctrl *get_pwr_ctrl(void);
void spm_code_swapping(void);
void spm_set_power_control(const struct pwr_ctrl *pwrctrl);
void spm_register_init(void);
void spm_reset_and_init_pcm(void);
void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
void spm_extern_initialize(void);
int spm_init(void);
#endif /* SOC_MEDIATEK_SPM_COMMON_H */ #endif /* SOC_MEDIATEK_SPM_COMMON_H */

165
src/soc/mediatek/common/spm.c
View File

@ -2,14 +2,116 @@
#include <assert.h> #include <assert.h>
#include <console/console.h> #include <console/console.h>
#include <delay.h>
#include <soc/mcu_common.h> #include <soc/mcu_common.h>
#include <soc/spm.h> #include <soc/spm.h>
#include <soc/spm_common.h> #include <soc/symbols.h>
#include <string.h> #include <string.h>
#include <timer.h>
#define SPMFW_HEADER_SIZE 16 #define SPMFW_HEADER_SIZE 16
void spm_parse_firmware(struct mtk_mcu *mcu) __weak void spm_extern_initialize(void) { /* do nothing */ }
static void spm_set_sysclk_settle(void)
{
write32(&mtk_spm->spm_clk_settle, SPM_SYSCLK_SETTLE);
}
static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm)
{
uintptr_t ptr;
u32 dmem_words;
u32 pmem_words;
u32 total_words;
u32 pmem_start;
u32 dmem_start;
ptr = (uintptr_t)pcm->buf + SPM_SYSTEM_BASE_OFFSET;
pmem_words = pcm->desc.pmem_words;
total_words = pcm->desc.total_words;
dmem_words = total_words - pmem_words;
pmem_start = pcm->desc.pmem_start;
dmem_start = pcm->desc.dmem_start;
printk(BIOS_DEBUG, "%s: ptr = %#lx, pmem/dmem words = %#x/%#x\n",
__func__, (long)ptr, pmem_words, dmem_words);
/* DMA needs 16-byte aligned source data. */
assert(ptr % 16 == 0);
write32(&mtk_spm->md32pcm_dma0_src, ptr);
write32(&mtk_spm->md32pcm_dma0_dst, pmem_start);
write32(&mtk_spm->md32pcm_dma0_wppt, pmem_words);
write32(&mtk_spm->md32pcm_dma0_wpto, dmem_start);
write32(&mtk_spm->md32pcm_dma0_count, total_words);
write32(&mtk_spm->md32pcm_dma0_con, MD32PCM_DMA0_CON_VAL);
write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL);
setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
}
static void spm_init_pcm_register(void)
{
/* Init r0 with POWER_ON_VAL0 */
write32(&mtk_spm->pcm_reg_data_ini,
read32(&mtk_spm->spm_power_on_val0));
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0);
write32(&mtk_spm->pcm_pwr_io_en, 0);
/* Init r7 with POWER_ON_VAL1 */
write32(&mtk_spm->pcm_reg_data_ini,
read32(&mtk_spm->spm_power_on_val1));
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
write32(&mtk_spm->pcm_pwr_io_en, 0);
}
static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl)
{
u32 pcm_flags = pwrctrl->pcm_flags, pcm_flags1 = pwrctrl->pcm_flags1;
/* Set PCM flags and data */
if (pwrctrl->pcm_flags_cust_clr != 0)
pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
if (pwrctrl->pcm_flags_cust_set != 0)
pcm_flags |= pwrctrl->pcm_flags_cust_set;
if (pwrctrl->pcm_flags1_cust_clr != 0)
pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
if (pwrctrl->pcm_flags1_cust_set != 0)
pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
write32(&mtk_spm->spm_sw_flag_0, pcm_flags);
write32(&mtk_spm->spm_sw_flag_1, pcm_flags1);
write32(&mtk_spm->spm_sw_rsv_7, pcm_flags);
write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1);
}
static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl)
{
/* Waiting for loading SPMFW done*/
while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0)
;
/* Init register to match PCM expectation */
write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF);
write32(&mtk_spm->spm_bus_protect2_mask_b,
SPM_BUS_PROTECT2_MASK_B_DEF);
write32(&mtk_spm->pcm_reg_data_ini, 0);
spm_set_pcm_flags(pwrctrl);
/* Kick PCM to run (only toggle PCM_KICK) */
setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
/* Reset md32pcm */
SET32_BITFIELDS(&mtk_spm->md32pcm_cfgreg_sw_rstn,
MD32PCM_CFGREG_SW_RSTN_RESET, 1);
/* Waiting for SPM init done */
udelay(SPM_INIT_DONE_US);
}
static void spm_parse_firmware(struct mtk_mcu *mcu)
{ {
size_t file_size, copy_size; size_t file_size, copy_size;
int offset; int offset;
@ -54,3 +156,62 @@ void spm_parse_firmware(struct mtk_mcu *mcu)
(int)(file_size - offset), (int)(file_size - offset),
(u8 *)mcu->load_buffer + offset); (u8 *)mcu->load_buffer + offset);
} }
static void reset_spm(struct mtk_mcu *mcu)
{
struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)mcu->priv;
const struct pwr_ctrl *spm_init_ctrl = get_pwr_ctrl();
spm_parse_firmware(mcu);
spm_reset_and_init_pcm();
spm_kick_im_to_fetch(pcm);
spm_init_pcm_register();
spm_set_wakeup_event(spm_init_ctrl);
spm_kick_pcm_to_run(spm_init_ctrl);
}
static struct mtk_mcu spm = {
.firmware_name = CONFIG_SPM_FIRMWARE,
.reset = reset_spm,
};
void spm_code_swapping(void)
{
u32 mask;
mask = read32(&mtk_spm->spm_wakeup_event_mask);
write32(&mtk_spm->spm_wakeup_event_mask,
mask & ~SPM_WAKEUP_EVENT_MASK_BIT0);
write32(&mtk_spm->spm_cpu_wakeup_event, 1);
write32(&mtk_spm->spm_cpu_wakeup_event, 0);
write32(&mtk_spm->spm_wakeup_event_mask, mask);
}
int spm_init(void)
{
struct dyna_load_pcm pcm;
struct stopwatch sw;
const struct pwr_ctrl *spm_init_ctrl = get_pwr_ctrl();
stopwatch_init(&sw);
spm_register_init();
spm_set_power_control(spm_init_ctrl);
spm_set_sysclk_settle();
spm_extern_initialize();
spm.load_buffer = _dram_dma;
spm.buffer_size = REGION_SIZE(dram_dma);
spm.priv = (void *)&pcm;
if (mtk_init_mcu(&spm)) {
printk(BIOS_ERR, "SPM: %s: failed in mtk_init_mcu\n", __func__);
return -1;
}
printk(BIOS_INFO, "SPM: %s done in %ld msecs, spm pc = %#x\n",
__func__, stopwatch_duration_msecs(&sw),
read32(&mtk_spm->md32pcm_pc));
return 0;
}

49
src/soc/mediatek/mt8186/include/soc/spm.h
View File

@ -11,6 +11,7 @@
#include <device/mmio.h> #include <device/mmio.h>
#include <soc/addressmap.h> #include <soc/addressmap.h>
#include <soc/mtcmos.h> #include <soc/mtcmos.h>
#include <soc/spm_common.h>
#include <types.h> #include <types.h>
#define SPM_INIT_DONE_US 20 #define SPM_INIT_DONE_US 20
@ -22,19 +23,7 @@
#define AP_PLL_CON3 (APMIXED_BASE + 0xC) #define AP_PLL_CON3 (APMIXED_BASE + 0xC)
#define AP_PLL_CON4 (APMIXED_BASE + 0x10) #define AP_PLL_CON4 (APMIXED_BASE + 0x10)
/* MD32PCM ADDR for SPM code fetch */ /* MD32PCM setting for SPM code fetch */
#define MD32PCM_BASE (SPM_BASE + 0x0A00)
#define MD32PCM_CFGREG_SW_RSTN (MD32PCM_BASE + 0x0000)
#define MD32PCM_DMA0_SRC (MD32PCM_BASE + 0x0200)
#define MD32PCM_DMA0_DST (MD32PCM_BASE + 0x0204)
#define MD32PCM_DMA0_WPPT (MD32PCM_BASE + 0x0208)
#define MD32PCM_DMA0_WPTO (MD32PCM_BASE + 0x020C)
#define MD32PCM_DMA0_COUNT (MD32PCM_BASE + 0x0210)
#define MD32PCM_DMA0_CON (MD32PCM_BASE + 0x0214)
#define MD32PCM_DMA0_START (MD32PCM_BASE + 0x0218)
#define MD32PCM_DMA0_RLCT (MD32PCM_BASE + 0x0224)
#define MD32PCM_INTC_IRQ_RAW_STA (MD32PCM_BASE + 0x033C)
#define MD32PCM_CFGREG_SW_RSTN_RUN 1 #define MD32PCM_CFGREG_SW_RSTN_RUN 1
#define MD32PCM_DMA0_CON_VAL 0x0003820E #define MD32PCM_DMA0_CON_VAL 0x0003820E
#define MD32PCM_DMA0_START_VAL 0x00008000 #define MD32PCM_DMA0_START_VAL 0x00008000
@ -649,6 +638,17 @@ struct mtk_spm_regs {
uint32_t ssusb_top_p1_pwr_con; uint32_t ssusb_top_p1_pwr_con;
uint32_t adsp_infra_pwr_con; uint32_t adsp_infra_pwr_con;
uint32_t adsp_ao_pwr_con; uint32_t adsp_ao_pwr_con;
uint32_t md32pcm_cfgreg_sw_rstn;
uint8_t reserved_6a04[0x200 - 4];
uint32_t md32pcm_dma0_src;
uint32_t md32pcm_dma0_dst;
uint32_t md32pcm_dma0_wppt;
uint32_t md32pcm_dma0_wpto;
uint32_t md32pcm_dma0_count;
uint32_t md32pcm_dma0_con;
uint32_t md32pcm_dma0_start;
uint8_t reserved_6c1c[8];
uint32_t md32pcm_dma0_rlct;
}; };
struct pwr_ctrl { struct pwr_ctrl {
@ -842,18 +842,15 @@ check_member(mtk_spm_regs, ssusb_top_pwr_con, 0x9F0);
check_member(mtk_spm_regs, ssusb_top_p1_pwr_con, 0x9F4); check_member(mtk_spm_regs, ssusb_top_p1_pwr_con, 0x9F4);
check_member(mtk_spm_regs, adsp_infra_pwr_con, 0x9F8); check_member(mtk_spm_regs, adsp_infra_pwr_con, 0x9F8);
check_member(mtk_spm_regs, adsp_ao_pwr_con, 0x9FC); check_member(mtk_spm_regs, adsp_ao_pwr_con, 0x9FC);
check_member(mtk_spm_regs, md32pcm_cfgreg_sw_rstn, 0xA00);
struct pcm_desc { check_member(mtk_spm_regs, md32pcm_dma0_src, 0xC00);
uint32_t pmem_words; check_member(mtk_spm_regs, md32pcm_dma0_dst, 0xC04);
uint32_t total_words; check_member(mtk_spm_regs, md32pcm_dma0_wppt, 0xC08);
uint32_t pmem_start; check_member(mtk_spm_regs, md32pcm_dma0_wpto, 0xC0C);
uint32_t dmem_start; check_member(mtk_spm_regs, md32pcm_dma0_count, 0xC10);
}; check_member(mtk_spm_regs, md32pcm_dma0_con, 0xC14);
check_member(mtk_spm_regs, md32pcm_dma0_start, 0xC18);
struct dyna_load_pcm { check_member(mtk_spm_regs, md32pcm_dma0_rlct, 0xC24);
u8 *buf; /* binary array */
struct pcm_desc desc;
};
static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;
@ -870,6 +867,4 @@ static const struct power_domain_data disp[] = {
static const struct power_domain_data audio[] = { static const struct power_domain_data audio[] = {
}; };
int spm_init(void);
#endif /* SOC_MEDIATEK_MT8186_SPM_H */ #endif /* SOC_MEDIATEK_MT8186_SPM_H */

172
src/soc/mediatek/mt8186/spm.c
View File

@ -6,15 +6,8 @@
*/ */
#include <assert.h> #include <assert.h>
#include <console/console.h>
#include <delay.h>
#include <soc/mcu_common.h> #include <soc/mcu_common.h>
#include <soc/spm.h> #include <soc/spm.h>
#include <soc/spm_common.h>
#include <soc/symbols.h>
#include <timer.h>
#define SPM_SYSTEM_BASE_OFFSET 0x40000000
static const struct pwr_ctrl spm_init_ctrl = { static const struct pwr_ctrl spm_init_ctrl = {
/* For SPM, this flag is not auto-gen. */ /* For SPM, this flag is not auto-gen. */
@ -187,7 +180,7 @@ static const struct pwr_ctrl spm_init_ctrl = {
/* Auto-gen End */ /* Auto-gen End */
}; };
static void spm_set_power_control(const struct pwr_ctrl *pwrctrl) void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
{ {
/* Auto-gen Start */ /* Auto-gen Start */
@ -383,7 +376,7 @@ static void spm_hw_s1_state_monitor(int en)
SPM_ACK_CHK_3_CON_EN_1, 0); SPM_ACK_CHK_3_CON_EN_1, 0);
} }
static void spm_register_init(void) void spm_register_init(void)
{ {
/* Enable register control */ /* Enable register control */
write32(&mtk_spm->poweron_config_set, write32(&mtk_spm->poweron_config_set,
@ -450,36 +443,19 @@ static void spm_register_init(void)
spm_hw_s1_state_monitor(0); spm_hw_s1_state_monitor(0);
} }
static void spm_extern_initialize(void) void spm_extern_initialize(void)
{ {
SET32_BITFIELDS(&mtk_spm->spm_dvfs_misc, SET32_BITFIELDS(&mtk_spm->spm_dvfs_misc,
INFRA_AO_RES_CTRL_MASK_EMI_IDLE, 1, INFRA_AO_RES_CTRL_MASK_EMI_IDLE, 1,
INFRA_AO_RES_CTRL_MASK_MPU_IDLE, 1); INFRA_AO_RES_CTRL_MASK_MPU_IDLE, 1);
} }
static void spm_set_sysclk_settle(void) void spm_reset_and_init_pcm(void)
{
write32(&mtk_spm->spm_clk_settle, SPM_SYSCLK_SETTLE);
}
static void spm_code_swapping(void)
{
u32 mask;
mask = read32(&mtk_spm->spm_wakeup_event_mask);
write32(&mtk_spm->spm_wakeup_event_mask,
mask & ~SPM_WAKEUP_EVENT_MASK_BIT0);
write32(&mtk_spm->spm_cpu_wakeup_event, 1);
write32(&mtk_spm->spm_cpu_wakeup_event, 0);
write32(&mtk_spm->spm_wakeup_event_mask, mask);
}
static void spm_reset_and_init_pcm(void)
{ {
bool first_load_fw = true; bool first_load_fw = true;
/* Check whether the SPM FW is running */ /* Check whether the SPM FW is running */
if (read32((void *)MD32PCM_CFGREG_SW_RSTN) & MD32PCM_CFGREG_SW_RSTN_RUN) if (read32(&mtk_spm->md32pcm_cfgreg_sw_rstn) & MD32PCM_CFGREG_SW_RSTN_RUN)
first_load_fw = false; first_load_fw = false;
if (!first_load_fw) { if (!first_load_fw) {
@ -506,55 +482,7 @@ static void spm_reset_and_init_pcm(void)
SPM_REGWR_CFG_KEY | RG_AHBMIF_APBEN_LSB | REG_MD32_APB_INTERNAL_EN_LSB); SPM_REGWR_CFG_KEY | RG_AHBMIF_APBEN_LSB | REG_MD32_APB_INTERNAL_EN_LSB);
} }
static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm) void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
{
uintptr_t ptr;
u32 dmem_words;
u32 pmem_words;
u32 total_words;
u32 pmem_start;
u32 dmem_start;
ptr = (uintptr_t)pcm->buf + SPM_SYSTEM_BASE_OFFSET;
pmem_words = pcm->desc.pmem_words;
total_words = pcm->desc.total_words;
dmem_words = total_words - pmem_words;
pmem_start = pcm->desc.pmem_start;
dmem_start = pcm->desc.dmem_start;
printk(BIOS_DEBUG, "%s: ptr = %#lx, pmem/dmem words = %#x/%#x\n",
__func__, (long)ptr, pmem_words, dmem_words);
/* DMA needs 16-byte aligned source data. */
assert(ptr % 16 == 0);
write32((void *)MD32PCM_DMA0_SRC, ptr);
write32((void *)MD32PCM_DMA0_DST, pmem_start);
write32((void *)MD32PCM_DMA0_WPPT, pmem_words);
write32((void *)MD32PCM_DMA0_WPTO, dmem_start);
write32((void *)MD32PCM_DMA0_COUNT, total_words);
write32((void *)MD32PCM_DMA0_CON, MD32PCM_DMA0_CON_VAL);
write32((void *)MD32PCM_DMA0_START, MD32PCM_DMA0_START_VAL);
setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
}
static void spm_init_pcm_register(void)
{
/* Init r0 with POWER_ON_VAL0 */
write32(&mtk_spm->pcm_reg_data_ini,
read32(&mtk_spm->spm_power_on_val0));
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0);
write32(&mtk_spm->pcm_pwr_io_en, 0);
/* Init r7 with POWER_ON_VAL1 */
write32(&mtk_spm->pcm_reg_data_ini,
read32(&mtk_spm->spm_power_on_val1));
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
write32(&mtk_spm->pcm_pwr_io_en, 0);
}
static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
{ {
u32 val, mask; u32 val, mask;
@ -596,91 +524,7 @@ static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
SYS_TIMER_START_EN_LSB, 0); SYS_TIMER_START_EN_LSB, 0);
} }
static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl) const struct pwr_ctrl *get_pwr_ctrl(void)
{ {
u32 pcm_flags = pwrctrl->pcm_flags, pcm_flags1 = pwrctrl->pcm_flags1; return &spm_init_ctrl;
/* Set PCM flags and data */
if (pwrctrl->pcm_flags_cust_clr != 0)
pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
if (pwrctrl->pcm_flags_cust_set != 0)
pcm_flags |= pwrctrl->pcm_flags_cust_set;
if (pwrctrl->pcm_flags1_cust_clr != 0)
pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
if (pwrctrl->pcm_flags1_cust_set != 0)
pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
write32(&mtk_spm->spm_sw_flag_0, pcm_flags);
write32(&mtk_spm->spm_sw_flag_1, pcm_flags1);
write32(&mtk_spm->spm_sw_rsv_7, pcm_flags);
write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1);
}
static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl)
{
/* Waiting for loading SPMFW done*/
while (read32((void *)MD32PCM_DMA0_RLCT) != 0x0)
;
/* Init register to match PCM expectation */
write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF);
write32(&mtk_spm->spm_bus_protect2_mask_b, SPM_BUS_PROTECT2_MASK_B_DEF);
write32(&mtk_spm->pcm_reg_data_ini, 0);
spm_set_pcm_flags(pwrctrl);
/* Kick PCM to run (only toggle PCM_KICK) */
setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
/* Reset md32pcm */
SET32_BITFIELDS((void *)MD32PCM_CFGREG_SW_RSTN,
MD32PCM_CFGREG_SW_RSTN_RESET, 1);
/* Waiting for SPM init done */
udelay(SPM_INIT_DONE_US);
}
static void reset_spm(struct mtk_mcu *mcu)
{
struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)mcu->priv;
spm_parse_firmware(mcu);
spm_reset_and_init_pcm();
spm_kick_im_to_fetch(pcm);
spm_init_pcm_register();
spm_set_wakeup_event(&spm_init_ctrl);
spm_kick_pcm_to_run(&spm_init_ctrl);
}
static struct mtk_mcu spm = {
.firmware_name = CONFIG_SPM_FIRMWARE,
.reset = reset_spm,
};
int spm_init(void)
{
struct dyna_load_pcm pcm;
struct stopwatch sw;
stopwatch_init(&sw);
spm_register_init();
spm_set_power_control(&spm_init_ctrl);
spm_set_sysclk_settle();
spm_extern_initialize();
spm.load_buffer = _dram_dma;
spm.buffer_size = REGION_SIZE(dram_dma);
spm.priv = (void *)&pcm;
if (mtk_init_mcu(&spm)) {
printk(BIOS_ERR, "SPM: %s: failed in mtk_init_mcu\n", __func__);
return -1;
}
printk(BIOS_INFO, "SPM: %s done in %ld msecs, spm pc = %#x\n",
__func__, stopwatch_duration_msecs(&sw),
read32(&mtk_spm->md32pcm_pc));
return 0;
} }

18
src/soc/mediatek/mt8192/include/soc/spm.h
View File

@ -3,8 +3,10 @@
#ifndef SOC_MEDIATEK_MT8192_SPM_H #ifndef SOC_MEDIATEK_MT8192_SPM_H
#define SOC_MEDIATEK_MT8192_SPM_H #define SOC_MEDIATEK_MT8192_SPM_H
#include <device/mmio.h>
#include <soc/addressmap.h> #include <soc/addressmap.h>
#include <soc/mtcmos.h> #include <soc/mtcmos.h>
#include <soc/spm_common.h>
#include <types.h> #include <types.h>
/* SPM READ/WRITE CFG */ /* SPM READ/WRITE CFG */
@ -51,7 +53,7 @@
#define SYS_TIMER_START_EN_LSB (1U << 0) /* 1b */ #define SYS_TIMER_START_EN_LSB (1U << 0) /* 1b */
/* MD32PCM_CFGREG_SW_RSTN (0x10006000+0xA00) */ /* MD32PCM_CFGREG_SW_RSTN (0x10006000+0xA00) */
#define MD32PCM_CFGREG_SW_RSTN_RESET (1U << 0) /* 1b */ DEFINE_BIT(MD32PCM_CFGREG_SW_RSTN_RESET, 0)
/************************************** /**************************************
* Config and Parameter * Config and Parameter
@ -660,20 +662,6 @@ check_member(mtk_spm_regs, md32pcm_dma0_rlct, 0xc24);
static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;
struct pcm_desc {
u32 pmem_words;
u32 total_words;
u32 pmem_start;
u32 dmem_start;
};
struct dyna_load_pcm {
u8 *buf; /* binary array */
struct pcm_desc desc;
};
int spm_init(void);
static const struct power_domain_data disp[] = { static const struct power_domain_data disp[] = {
{ {
.pwr_con = &mtk_spm->dis_pwr_con, .pwr_con = &mtk_spm->dis_pwr_con,

172
src/soc/mediatek/mt8192/spm.c
View File

@ -1,16 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h> #include <assert.h>
#include <console/console.h>
#include <delay.h>
#include <device/mmio.h>
#include <soc/mcu_common.h> #include <soc/mcu_common.h>
#include <soc/spm.h> #include <soc/spm.h>
#include <soc/spm_common.h>
#include <soc/symbols.h>
#include <timer.h>
#define SPM_SYSTEM_BASE_OFFSET 0x40000000
static const struct pwr_ctrl spm_init_ctrl = { static const struct pwr_ctrl spm_init_ctrl = {
/* Auto-gen Start */ /* Auto-gen Start */
@ -127,7 +119,7 @@ static const struct pwr_ctrl spm_init_ctrl = {
/* Auto-gen End */ /* Auto-gen End */
}; };
static void spm_set_power_control(const struct pwr_ctrl *pwrctrl) void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
{ {
/* Auto-gen Start */ /* Auto-gen Start */
@ -307,7 +299,7 @@ static void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
/* Auto-gen End */ /* Auto-gen End */
} }
static void spm_register_init(void) void spm_register_init(void)
{ {
/* Enable register control */ /* Enable register control */
write32(&mtk_spm->poweron_config_set, write32(&mtk_spm->poweron_config_set,
@ -372,24 +364,7 @@ static void spm_register_init(void)
SPM_ACK_CHK_3_CON_CLR_ALL); SPM_ACK_CHK_3_CON_CLR_ALL);
} }
static void spm_set_sysclk_settle(void) void spm_reset_and_init_pcm(void)
{
write32(&mtk_spm->spm_clk_settle, SPM_SYSCLK_SETTLE);
}
static void spm_code_swapping(void)
{
u32 mask;
mask = read32(&mtk_spm->spm_wakeup_event_mask);
write32(&mtk_spm->spm_wakeup_event_mask,
mask & ~SPM_WAKEUP_EVENT_MASK_BIT0);
write32(&mtk_spm->spm_cpu_wakeup_event, 1);
write32(&mtk_spm->spm_cpu_wakeup_event, 0);
write32(&mtk_spm->spm_wakeup_event_mask, mask);
}
static void spm_reset_and_init_pcm(void)
{ {
bool first_load_fw = true; bool first_load_fw = true;
@ -424,58 +399,7 @@ static void spm_reset_and_init_pcm(void)
REG_MD32_APB_INTERNAL_EN_LSB); REG_MD32_APB_INTERNAL_EN_LSB);
} }
static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm) void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
{
uintptr_t ptr;
u32 dmem_words;
u32 pmem_words;
u32 total_words;
u32 pmem_start;
u32 dmem_start;
ptr = (uintptr_t)pcm->buf + SPM_SYSTEM_BASE_OFFSET;
pmem_words = pcm->desc.pmem_words;
total_words = pcm->desc.total_words;
dmem_words = total_words - pmem_words;
pmem_start = pcm->desc.pmem_start;
dmem_start = pcm->desc.dmem_start;
printk(BIOS_DEBUG, "%s: ptr = %#lx, pmem/dmem words = %#x/%#x\n",
__func__, (long)ptr, pmem_words, dmem_words);
/* DMA needs 16-byte aligned source data. */
assert(ptr % 16 == 0);
/* Program/Data must also be 16-byte (4-word) aligned. */
assert(pmem_words % 4 == 0);
assert(dmem_words % 4 == 0);
write32(&mtk_spm->md32pcm_dma0_src, ptr);
write32(&mtk_spm->md32pcm_dma0_dst, pmem_start);
write32(&mtk_spm->md32pcm_dma0_wppt, pmem_words);
write32(&mtk_spm->md32pcm_dma0_wpto, dmem_start);
write32(&mtk_spm->md32pcm_dma0_count, total_words);
write32(&mtk_spm->md32pcm_dma0_con, MD32PCM_DMA0_CON_VAL);
write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL);
setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
}
static void spm_init_pcm_register(void)
{
/* Init r0 with POWER_ON_VAL0 */
write32(&mtk_spm->pcm_reg_data_ini,
read32(&mtk_spm->spm_power_on_val0));
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0);
write32(&mtk_spm->pcm_pwr_io_en, 0);
/* Init r7 with POWER_ON_VAL1 */
write32(&mtk_spm->pcm_reg_data_ini,
read32(&mtk_spm->spm_power_on_val1));
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
write32(&mtk_spm->pcm_pwr_io_en, 0);
}
static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
{ {
u32 val, mask; u32 val, mask;
@ -519,91 +443,7 @@ static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
clrbits32(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB); clrbits32(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB);
} }
static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl) const struct pwr_ctrl *get_pwr_ctrl(void)
{ {
u32 pcm_flags = pwrctrl->pcm_flags, pcm_flags1 = pwrctrl->pcm_flags1; return &spm_init_ctrl;
/* Set PCM flags and data */
if (pwrctrl->pcm_flags_cust_clr != 0)
pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
if (pwrctrl->pcm_flags_cust_set != 0)
pcm_flags |= pwrctrl->pcm_flags_cust_set;
if (pwrctrl->pcm_flags1_cust_clr != 0)
pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
if (pwrctrl->pcm_flags1_cust_set != 0)
pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
write32(&mtk_spm->spm_sw_flag_0, pcm_flags);
write32(&mtk_spm->spm_sw_flag_1, pcm_flags1);
write32(&mtk_spm->spm_sw_rsv_7, pcm_flags);
write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1);
}
static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl)
{
/* Waiting for loading SPMFW done*/
while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0)
;
/* Init register to match PCM expectation */
write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF);
write32(&mtk_spm->spm_bus_protect2_mask_b,
SPM_BUS_PROTECT2_MASK_B_DEF);
write32(&mtk_spm->pcm_reg_data_ini, 0);
spm_set_pcm_flags(pwrctrl);
/* Kick PCM to run (only toggle PCM_KICK) */
setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
/* Reset md32pcm */
setbits32(&mtk_spm->md32pcm_cfgreg_sw_rstn,
MD32PCM_CFGREG_SW_RSTN_RESET);
/* Waiting for SPM init done */
udelay(SPM_INIT_DONE_US);
}
static void reset_spm(struct mtk_mcu *mcu)
{
struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)mcu->priv;
spm_parse_firmware(mcu);
spm_reset_and_init_pcm();
spm_kick_im_to_fetch(pcm);
spm_init_pcm_register();
spm_set_wakeup_event(&spm_init_ctrl);
spm_kick_pcm_to_run(&spm_init_ctrl);
}
static struct mtk_mcu spm = {
.firmware_name = CONFIG_SPM_FIRMWARE,
.reset = reset_spm,
};
int spm_init(void)
{
struct dyna_load_pcm pcm;
struct stopwatch sw;
stopwatch_init(&sw);
spm_register_init();
spm_set_power_control(&spm_init_ctrl);
spm_set_sysclk_settle();
spm.load_buffer = _dram_dma;
spm.buffer_size = REGION_SIZE(dram_dma);
spm.priv = (void *)&pcm;
if (mtk_init_mcu(&spm)) {
printk(BIOS_ERR, "SPM: %s: failed in mtk_init_mcu\n", __func__);
return -1;
}
printk(BIOS_INFO, "SPM: %s done in %ld msecs, spm pc = %#x\n",
__func__, stopwatch_duration_msecs(&sw),
read32(&mtk_spm->md32pcm_pc));
return 0;
} }

15
src/soc/mediatek/mt8195/include/soc/spm.h
View File

@ -6,6 +6,7 @@
#include <device/mmio.h> #include <device/mmio.h>
#include <soc/addressmap.h> #include <soc/addressmap.h>
#include <soc/mtcmos.h> #include <soc/mtcmos.h>
#include <soc/spm_common.h>
#include <types.h> #include <types.h>
/* SPM READ/WRITE CFG */ /* SPM READ/WRITE CFG */
@ -952,20 +953,6 @@ check_member(mtk_spm_regs, ulposc_con, 0x644);
static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;
struct pcm_desc {
u32 pmem_words;
u32 total_words;
u32 pmem_start;
u32 dmem_start;
};
struct dyna_load_pcm {
u8 *buf; /* binary array */
struct pcm_desc desc;
};
int spm_init(void);
static const struct power_domain_data disp[] = { static const struct power_domain_data disp[] = {
{ {
.pwr_con = &mtk_spm->vppsys0_pwr_con, .pwr_con = &mtk_spm->vppsys0_pwr_con,

169
src/soc/mediatek/mt8195/spm.c
View File

@ -1,16 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h> #include <assert.h>
#include <console/console.h>
#include <delay.h>
#include <device/mmio.h>
#include <soc/mcu_common.h> #include <soc/mcu_common.h>
#include <soc/spm.h> #include <soc/spm.h>
#include <soc/spm_common.h>
#include <soc/symbols.h>
#include <timer.h>
#define SPM_SYSTEM_BASE_OFFSET 0x40000000
static const struct pwr_ctrl spm_init_ctrl = { static const struct pwr_ctrl spm_init_ctrl = {
.pcm_flags = SPM_FLAG_DISABLE_VCORE_DVS | SPM_FLAG_DISABLE_VCORE_DFS | .pcm_flags = SPM_FLAG_DISABLE_VCORE_DVS | SPM_FLAG_DISABLE_VCORE_DFS |
@ -284,7 +276,7 @@ static const struct pwr_ctrl spm_init_ctrl = {
.reg_ext_wakeup_event_mask = 0xFFFFFFFF, .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
}; };
static void spm_set_power_control(const struct pwr_ctrl *pwrctrl) void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
{ {
/* Auto-gen Start */ /* Auto-gen Start */
@ -423,7 +415,7 @@ static void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
/* Auto-gen End */ /* Auto-gen End */
} }
static void spm_register_init(void) void spm_register_init(void)
{ {
/* Enable register control */ /* Enable register control */
write32(&mtk_spm->poweron_config_set, write32(&mtk_spm->poweron_config_set,
@ -478,24 +470,7 @@ static void spm_register_init(void)
} }
static void spm_set_sysclk_settle(void) void spm_reset_and_init_pcm(void)
{
write32(&mtk_spm->spm_clk_settle, SPM_SYSCLK_SETTLE);
}
static void spm_code_swapping(void)
{
u32 mask;
mask = read32(&mtk_spm->spm_wakeup_event_mask);
write32(&mtk_spm->spm_wakeup_event_mask,
mask & ~SPM_WAKEUP_EVENT_MASK_BIT0);
write32(&mtk_spm->spm_cpu_wakeup_event, 1);
write32(&mtk_spm->spm_cpu_wakeup_event, 0);
write32(&mtk_spm->spm_wakeup_event_mask, mask);
}
static void spm_reset_and_init_pcm(void)
{ {
bool first_load_fw = true; bool first_load_fw = true;
@ -530,55 +505,7 @@ static void spm_reset_and_init_pcm(void)
REG_MD32_APB_INTERNAL_EN_LSB); REG_MD32_APB_INTERNAL_EN_LSB);
} }
static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm) void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
{
uintptr_t ptr;
u32 dmem_words;
u32 pmem_words;
u32 total_words;
u32 pmem_start;
u32 dmem_start;
ptr = (uintptr_t)pcm->buf + SPM_SYSTEM_BASE_OFFSET;
pmem_words = pcm->desc.pmem_words;
total_words = pcm->desc.total_words;
dmem_words = total_words - pmem_words;
pmem_start = pcm->desc.pmem_start;
dmem_start = pcm->desc.dmem_start;
printk(BIOS_DEBUG, "%s: ptr = %#lx, pmem/dmem words = %#x/%#x\n",
__func__, (long)ptr, pmem_words, dmem_words);
/* DMA needs 16-byte aligned source data. */
assert(ptr % 16 == 0);
write32(&mtk_spm->md32pcm_dma0_src, ptr);
write32(&mtk_spm->md32pcm_dma0_dst, pmem_start);
write32(&mtk_spm->md32pcm_dma0_wppt, pmem_words);
write32(&mtk_spm->md32pcm_dma0_wpto, dmem_start);
write32(&mtk_spm->md32pcm_dma0_count, total_words);
write32(&mtk_spm->md32pcm_dma0_con, MD32PCM_DMA0_CON_VAL);
write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL);
setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
}
static void spm_init_pcm_register(void)
{
/* Init r0 with POWER_ON_VAL0 */
write32(&mtk_spm->pcm_reg_data_ini,
read32(&mtk_spm->spm_power_on_val0));
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0);
write32(&mtk_spm->pcm_pwr_io_en, 0);
/* Init r7 with POWER_ON_VAL1 */
write32(&mtk_spm->pcm_reg_data_ini,
read32(&mtk_spm->spm_power_on_val1));
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
write32(&mtk_spm->pcm_pwr_io_en, 0);
}
static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
{ {
u32 val, mask; u32 val, mask;
@ -623,91 +550,7 @@ static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
SYS_TIMER_START_EN_LSB, 0); SYS_TIMER_START_EN_LSB, 0);
} }
static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl) const struct pwr_ctrl *get_pwr_ctrl(void)
{ {
u32 pcm_flags = pwrctrl->pcm_flags, pcm_flags1 = pwrctrl->pcm_flags1; return &spm_init_ctrl;
/* Set PCM flags and data */
if (pwrctrl->pcm_flags_cust_clr != 0)
pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
if (pwrctrl->pcm_flags_cust_set != 0)
pcm_flags |= pwrctrl->pcm_flags_cust_set;
if (pwrctrl->pcm_flags1_cust_clr != 0)
pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
if (pwrctrl->pcm_flags1_cust_set != 0)
pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
write32(&mtk_spm->spm_sw_flag_0, pcm_flags);
write32(&mtk_spm->spm_sw_flag_1, pcm_flags1);
write32(&mtk_spm->spm_sw_rsv_7, pcm_flags);
write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1);
}
static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl)
{
/* Waiting for loading SPMFW done*/
while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0)
;
/* Init register to match PCM expectation */
write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF);
write32(&mtk_spm->spm_bus_protect2_mask_b,
SPM_BUS_PROTECT2_MASK_B_DEF);
write32(&mtk_spm->pcm_reg_data_ini, 0);
spm_set_pcm_flags(pwrctrl);
/* Kick PCM to run (only toggle PCM_KICK) */
setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
/* Reset md32pcm */
SET32_BITFIELDS(&mtk_spm->md32pcm_cfgreg_sw_rstn,
MD32PCM_CFGREG_SW_RSTN_RESET, 1);
/* Waiting for SPM init done */
udelay(SPM_INIT_DONE_US);
}
static void reset_spm(struct mtk_mcu *mcu)
{
struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)mcu->priv;
spm_parse_firmware(mcu);
spm_reset_and_init_pcm();
spm_kick_im_to_fetch(pcm);
spm_init_pcm_register();
spm_set_wakeup_event(&spm_init_ctrl);
spm_kick_pcm_to_run(&spm_init_ctrl);
}
static struct mtk_mcu spm = {
.firmware_name = CONFIG_SPM_FIRMWARE,
.reset = reset_spm,
};
int spm_init(void)
{
struct dyna_load_pcm pcm;
struct stopwatch sw;
stopwatch_init(&sw);
spm_register_init();
spm_set_power_control(&spm_init_ctrl);
spm_set_sysclk_settle();
spm.load_buffer = _dram_dma;
spm.buffer_size = REGION_SIZE(dram_dma);
spm.priv = (void *)&pcm;
if (mtk_init_mcu(&spm)) {
printk(BIOS_ERR, "SPM: %s: failed in mtk_init_mcu\n", __func__);
return -1;
}
printk(BIOS_INFO, "SPM: %s done in %ld msecs, spm pc = %#x\n",
__func__, stopwatch_duration_msecs(&sw),
read32(&mtk_spm->md32pcm_pc));
return 0;
} }