soc/mediatek: Move some SPM functions to common
Some functions are the same in spm.c for MT8192, MT8195, MT8186 and MT8188, so we move them to common/spm.c. TEST=build pass. BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I29ddefc47d8bd156fa1ca0cedd4deaed676ae7e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Bo-Chen Chen
Felix Held
parent
dcdbda5c93
commit
9d638a9516
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@ -5,5 +5,27 @@
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#include <soc/mcu_common.h>
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void spm_parse_firmware(struct mtk_mcu *mcu);
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#define SPM_SYSTEM_BASE_OFFSET 0x40000000
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struct pcm_desc {
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u32 pmem_words;
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u32 total_words;
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u32 pmem_start;
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u32 dmem_start;
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};
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struct dyna_load_pcm {
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u8 *buf; /* binary array */
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struct pcm_desc desc;
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};
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const struct pwr_ctrl *get_pwr_ctrl(void);
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void spm_code_swapping(void);
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void spm_set_power_control(const struct pwr_ctrl *pwrctrl);
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void spm_register_init(void);
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void spm_reset_and_init_pcm(void);
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void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
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void spm_extern_initialize(void);
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int spm_init(void);
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#endif /* SOC_MEDIATEK_SPM_COMMON_H */
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@ -2,14 +2,116 @@
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#include <assert.h>
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#include <console/console.h>
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#include <delay.h>
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#include <soc/mcu_common.h>
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#include <soc/spm.h>
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#include <soc/spm_common.h>
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#include <soc/symbols.h>
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#include <string.h>
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#include <timer.h>
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#define SPMFW_HEADER_SIZE 16
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void spm_parse_firmware(struct mtk_mcu *mcu)
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__weak void spm_extern_initialize(void) { /* do nothing */ }
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static void spm_set_sysclk_settle(void)
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{
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write32(&mtk_spm->spm_clk_settle, SPM_SYSCLK_SETTLE);
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}
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static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm)
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{
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uintptr_t ptr;
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u32 dmem_words;
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u32 pmem_words;
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u32 total_words;
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u32 pmem_start;
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u32 dmem_start;
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ptr = (uintptr_t)pcm->buf + SPM_SYSTEM_BASE_OFFSET;
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pmem_words = pcm->desc.pmem_words;
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total_words = pcm->desc.total_words;
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dmem_words = total_words - pmem_words;
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pmem_start = pcm->desc.pmem_start;
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dmem_start = pcm->desc.dmem_start;
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printk(BIOS_DEBUG, "%s: ptr = %#lx, pmem/dmem words = %#x/%#x\n",
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__func__, (long)ptr, pmem_words, dmem_words);
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/* DMA needs 16-byte aligned source data. */
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assert(ptr % 16 == 0);
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write32(&mtk_spm->md32pcm_dma0_src, ptr);
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write32(&mtk_spm->md32pcm_dma0_dst, pmem_start);
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write32(&mtk_spm->md32pcm_dma0_wppt, pmem_words);
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write32(&mtk_spm->md32pcm_dma0_wpto, dmem_start);
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write32(&mtk_spm->md32pcm_dma0_count, total_words);
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write32(&mtk_spm->md32pcm_dma0_con, MD32PCM_DMA0_CON_VAL);
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write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL);
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setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
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}
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static void spm_init_pcm_register(void)
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{
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/* Init r0 with POWER_ON_VAL0 */
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write32(&mtk_spm->pcm_reg_data_ini,
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read32(&mtk_spm->spm_power_on_val0));
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write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0);
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write32(&mtk_spm->pcm_pwr_io_en, 0);
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/* Init r7 with POWER_ON_VAL1 */
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write32(&mtk_spm->pcm_reg_data_ini,
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read32(&mtk_spm->spm_power_on_val1));
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write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
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write32(&mtk_spm->pcm_pwr_io_en, 0);
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}
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static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl)
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{
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u32 pcm_flags = pwrctrl->pcm_flags, pcm_flags1 = pwrctrl->pcm_flags1;
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/* Set PCM flags and data */
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if (pwrctrl->pcm_flags_cust_clr != 0)
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pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
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if (pwrctrl->pcm_flags_cust_set != 0)
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pcm_flags |= pwrctrl->pcm_flags_cust_set;
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if (pwrctrl->pcm_flags1_cust_clr != 0)
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pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
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if (pwrctrl->pcm_flags1_cust_set != 0)
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pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
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write32(&mtk_spm->spm_sw_flag_0, pcm_flags);
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write32(&mtk_spm->spm_sw_flag_1, pcm_flags1);
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write32(&mtk_spm->spm_sw_rsv_7, pcm_flags);
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write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1);
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}
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static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl)
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{
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/* Waiting for loading SPMFW done*/
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while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0)
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;
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/* Init register to match PCM expectation */
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write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF);
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write32(&mtk_spm->spm_bus_protect2_mask_b,
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SPM_BUS_PROTECT2_MASK_B_DEF);
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write32(&mtk_spm->pcm_reg_data_ini, 0);
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spm_set_pcm_flags(pwrctrl);
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/* Kick PCM to run (only toggle PCM_KICK) */
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setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
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/* Reset md32pcm */
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SET32_BITFIELDS(&mtk_spm->md32pcm_cfgreg_sw_rstn,
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MD32PCM_CFGREG_SW_RSTN_RESET, 1);
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/* Waiting for SPM init done */
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udelay(SPM_INIT_DONE_US);
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}
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static void spm_parse_firmware(struct mtk_mcu *mcu)
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{
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size_t file_size, copy_size;
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int offset;
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@ -54,3 +156,62 @@ void spm_parse_firmware(struct mtk_mcu *mcu)
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(int)(file_size - offset),
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(u8 *)mcu->load_buffer + offset);
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}
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static void reset_spm(struct mtk_mcu *mcu)
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{
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struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)mcu->priv;
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const struct pwr_ctrl *spm_init_ctrl = get_pwr_ctrl();
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spm_parse_firmware(mcu);
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spm_reset_and_init_pcm();
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spm_kick_im_to_fetch(pcm);
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spm_init_pcm_register();
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spm_set_wakeup_event(spm_init_ctrl);
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spm_kick_pcm_to_run(spm_init_ctrl);
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}
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static struct mtk_mcu spm = {
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.firmware_name = CONFIG_SPM_FIRMWARE,
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.reset = reset_spm,
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};
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void spm_code_swapping(void)
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{
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u32 mask;
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mask = read32(&mtk_spm->spm_wakeup_event_mask);
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write32(&mtk_spm->spm_wakeup_event_mask,
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mask & ~SPM_WAKEUP_EVENT_MASK_BIT0);
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write32(&mtk_spm->spm_cpu_wakeup_event, 1);
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write32(&mtk_spm->spm_cpu_wakeup_event, 0);
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write32(&mtk_spm->spm_wakeup_event_mask, mask);
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}
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int spm_init(void)
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{
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struct dyna_load_pcm pcm;
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struct stopwatch sw;
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const struct pwr_ctrl *spm_init_ctrl = get_pwr_ctrl();
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stopwatch_init(&sw);
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spm_register_init();
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spm_set_power_control(spm_init_ctrl);
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spm_set_sysclk_settle();
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spm_extern_initialize();
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spm.load_buffer = _dram_dma;
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spm.buffer_size = REGION_SIZE(dram_dma);
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spm.priv = (void *)&pcm;
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if (mtk_init_mcu(&spm)) {
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printk(BIOS_ERR, "SPM: %s: failed in mtk_init_mcu\n", __func__);
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return -1;
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}
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printk(BIOS_INFO, "SPM: %s done in %ld msecs, spm pc = %#x\n",
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__func__, stopwatch_duration_msecs(&sw),
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read32(&mtk_spm->md32pcm_pc));
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return 0;
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}
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@ -11,6 +11,7 @@
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#include <device/mmio.h>
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#include <soc/addressmap.h>
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#include <soc/mtcmos.h>
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#include <soc/spm_common.h>
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#include <types.h>
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#define SPM_INIT_DONE_US 20
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@ -22,19 +23,7 @@
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#define AP_PLL_CON3 (APMIXED_BASE + 0xC)
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#define AP_PLL_CON4 (APMIXED_BASE + 0x10)
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/* MD32PCM ADDR for SPM code fetch */
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#define MD32PCM_BASE (SPM_BASE + 0x0A00)
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#define MD32PCM_CFGREG_SW_RSTN (MD32PCM_BASE + 0x0000)
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#define MD32PCM_DMA0_SRC (MD32PCM_BASE + 0x0200)
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#define MD32PCM_DMA0_DST (MD32PCM_BASE + 0x0204)
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#define MD32PCM_DMA0_WPPT (MD32PCM_BASE + 0x0208)
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#define MD32PCM_DMA0_WPTO (MD32PCM_BASE + 0x020C)
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#define MD32PCM_DMA0_COUNT (MD32PCM_BASE + 0x0210)
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#define MD32PCM_DMA0_CON (MD32PCM_BASE + 0x0214)
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#define MD32PCM_DMA0_START (MD32PCM_BASE + 0x0218)
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#define MD32PCM_DMA0_RLCT (MD32PCM_BASE + 0x0224)
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#define MD32PCM_INTC_IRQ_RAW_STA (MD32PCM_BASE + 0x033C)
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/* MD32PCM setting for SPM code fetch */
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#define MD32PCM_CFGREG_SW_RSTN_RUN 1
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#define MD32PCM_DMA0_CON_VAL 0x0003820E
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#define MD32PCM_DMA0_START_VAL 0x00008000
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@ -649,6 +638,17 @@ struct mtk_spm_regs {
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uint32_t ssusb_top_p1_pwr_con;
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uint32_t adsp_infra_pwr_con;
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uint32_t adsp_ao_pwr_con;
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uint32_t md32pcm_cfgreg_sw_rstn;
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uint8_t reserved_6a04[0x200 - 4];
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uint32_t md32pcm_dma0_src;
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uint32_t md32pcm_dma0_dst;
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uint32_t md32pcm_dma0_wppt;
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uint32_t md32pcm_dma0_wpto;
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uint32_t md32pcm_dma0_count;
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uint32_t md32pcm_dma0_con;
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uint32_t md32pcm_dma0_start;
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uint8_t reserved_6c1c[8];
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uint32_t md32pcm_dma0_rlct;
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};
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struct pwr_ctrl {
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@ -842,18 +842,15 @@ check_member(mtk_spm_regs, ssusb_top_pwr_con, 0x9F0);
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check_member(mtk_spm_regs, ssusb_top_p1_pwr_con, 0x9F4);
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check_member(mtk_spm_regs, adsp_infra_pwr_con, 0x9F8);
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check_member(mtk_spm_regs, adsp_ao_pwr_con, 0x9FC);
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struct pcm_desc {
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uint32_t pmem_words;
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uint32_t total_words;
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uint32_t pmem_start;
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uint32_t dmem_start;
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};
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struct dyna_load_pcm {
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u8 *buf; /* binary array */
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struct pcm_desc desc;
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};
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check_member(mtk_spm_regs, md32pcm_cfgreg_sw_rstn, 0xA00);
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check_member(mtk_spm_regs, md32pcm_dma0_src, 0xC00);
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check_member(mtk_spm_regs, md32pcm_dma0_dst, 0xC04);
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check_member(mtk_spm_regs, md32pcm_dma0_wppt, 0xC08);
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check_member(mtk_spm_regs, md32pcm_dma0_wpto, 0xC0C);
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check_member(mtk_spm_regs, md32pcm_dma0_count, 0xC10);
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check_member(mtk_spm_regs, md32pcm_dma0_con, 0xC14);
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check_member(mtk_spm_regs, md32pcm_dma0_start, 0xC18);
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check_member(mtk_spm_regs, md32pcm_dma0_rlct, 0xC24);
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static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;
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@ -870,6 +867,4 @@ static const struct power_domain_data disp[] = {
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static const struct power_domain_data audio[] = {
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};
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int spm_init(void);
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#endif /* SOC_MEDIATEK_MT8186_SPM_H */
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@ -6,15 +6,8 @@
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*/
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#include <assert.h>
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#include <console/console.h>
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#include <delay.h>
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#include <soc/mcu_common.h>
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#include <soc/spm.h>
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#include <soc/spm_common.h>
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#include <soc/symbols.h>
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#include <timer.h>
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#define SPM_SYSTEM_BASE_OFFSET 0x40000000
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static const struct pwr_ctrl spm_init_ctrl = {
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/* For SPM, this flag is not auto-gen. */
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@ -187,7 +180,7 @@ static const struct pwr_ctrl spm_init_ctrl = {
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/* Auto-gen End */
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};
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static void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
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void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
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{
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/* Auto-gen Start */
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@ -383,7 +376,7 @@ static void spm_hw_s1_state_monitor(int en)
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SPM_ACK_CHK_3_CON_EN_1, 0);
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}
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static void spm_register_init(void)
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void spm_register_init(void)
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{
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/* Enable register control */
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write32(&mtk_spm->poweron_config_set,
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@ -450,36 +443,19 @@ static void spm_register_init(void)
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spm_hw_s1_state_monitor(0);
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}
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static void spm_extern_initialize(void)
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void spm_extern_initialize(void)
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{
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SET32_BITFIELDS(&mtk_spm->spm_dvfs_misc,
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INFRA_AO_RES_CTRL_MASK_EMI_IDLE, 1,
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INFRA_AO_RES_CTRL_MASK_MPU_IDLE, 1);
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}
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static void spm_set_sysclk_settle(void)
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{
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write32(&mtk_spm->spm_clk_settle, SPM_SYSCLK_SETTLE);
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}
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static void spm_code_swapping(void)
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{
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u32 mask;
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mask = read32(&mtk_spm->spm_wakeup_event_mask);
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write32(&mtk_spm->spm_wakeup_event_mask,
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mask & ~SPM_WAKEUP_EVENT_MASK_BIT0);
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write32(&mtk_spm->spm_cpu_wakeup_event, 1);
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write32(&mtk_spm->spm_cpu_wakeup_event, 0);
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write32(&mtk_spm->spm_wakeup_event_mask, mask);
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}
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static void spm_reset_and_init_pcm(void)
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void spm_reset_and_init_pcm(void)
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{
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bool first_load_fw = true;
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/* Check whether the SPM FW is running */
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if (read32((void *)MD32PCM_CFGREG_SW_RSTN) & MD32PCM_CFGREG_SW_RSTN_RUN)
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if (read32(&mtk_spm->md32pcm_cfgreg_sw_rstn) & MD32PCM_CFGREG_SW_RSTN_RUN)
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first_load_fw = false;
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if (!first_load_fw) {
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@ -506,55 +482,7 @@ static void spm_reset_and_init_pcm(void)
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SPM_REGWR_CFG_KEY | RG_AHBMIF_APBEN_LSB | REG_MD32_APB_INTERNAL_EN_LSB);
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}
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static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm)
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{
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uintptr_t ptr;
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u32 dmem_words;
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u32 pmem_words;
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u32 total_words;
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u32 pmem_start;
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u32 dmem_start;
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ptr = (uintptr_t)pcm->buf + SPM_SYSTEM_BASE_OFFSET;
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pmem_words = pcm->desc.pmem_words;
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total_words = pcm->desc.total_words;
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dmem_words = total_words - pmem_words;
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pmem_start = pcm->desc.pmem_start;
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dmem_start = pcm->desc.dmem_start;
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|
||||
printk(BIOS_DEBUG, "%s: ptr = %#lx, pmem/dmem words = %#x/%#x\n",
|
||||
__func__, (long)ptr, pmem_words, dmem_words);
|
||||
|
||||
/* DMA needs 16-byte aligned source data. */
|
||||
assert(ptr % 16 == 0);
|
||||
|
||||
write32((void *)MD32PCM_DMA0_SRC, ptr);
|
||||
write32((void *)MD32PCM_DMA0_DST, pmem_start);
|
||||
write32((void *)MD32PCM_DMA0_WPPT, pmem_words);
|
||||
write32((void *)MD32PCM_DMA0_WPTO, dmem_start);
|
||||
write32((void *)MD32PCM_DMA0_COUNT, total_words);
|
||||
write32((void *)MD32PCM_DMA0_CON, MD32PCM_DMA0_CON_VAL);
|
||||
write32((void *)MD32PCM_DMA0_START, MD32PCM_DMA0_START_VAL);
|
||||
|
||||
setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
|
||||
}
|
||||
|
||||
static void spm_init_pcm_register(void)
|
||||
{
|
||||
/* Init r0 with POWER_ON_VAL0 */
|
||||
write32(&mtk_spm->pcm_reg_data_ini,
|
||||
read32(&mtk_spm->spm_power_on_val0));
|
||||
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0);
|
||||
write32(&mtk_spm->pcm_pwr_io_en, 0);
|
||||
|
||||
/* Init r7 with POWER_ON_VAL1 */
|
||||
write32(&mtk_spm->pcm_reg_data_ini,
|
||||
read32(&mtk_spm->spm_power_on_val1));
|
||||
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
|
||||
write32(&mtk_spm->pcm_pwr_io_en, 0);
|
||||
}
|
||||
|
||||
static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
|
||||
void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
|
||||
{
|
||||
u32 val, mask;
|
||||
|
||||
|
|
@ -596,91 +524,7 @@ static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
|
|||
SYS_TIMER_START_EN_LSB, 0);
|
||||
}
|
||||
|
||||
static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl)
|
||||
const struct pwr_ctrl *get_pwr_ctrl(void)
|
||||
{
|
||||
u32 pcm_flags = pwrctrl->pcm_flags, pcm_flags1 = pwrctrl->pcm_flags1;
|
||||
|
||||
/* Set PCM flags and data */
|
||||
if (pwrctrl->pcm_flags_cust_clr != 0)
|
||||
pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
|
||||
if (pwrctrl->pcm_flags_cust_set != 0)
|
||||
pcm_flags |= pwrctrl->pcm_flags_cust_set;
|
||||
if (pwrctrl->pcm_flags1_cust_clr != 0)
|
||||
pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
|
||||
if (pwrctrl->pcm_flags1_cust_set != 0)
|
||||
pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
|
||||
|
||||
write32(&mtk_spm->spm_sw_flag_0, pcm_flags);
|
||||
write32(&mtk_spm->spm_sw_flag_1, pcm_flags1);
|
||||
write32(&mtk_spm->spm_sw_rsv_7, pcm_flags);
|
||||
write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1);
|
||||
}
|
||||
|
||||
static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl)
|
||||
{
|
||||
/* Waiting for loading SPMFW done*/
|
||||
while (read32((void *)MD32PCM_DMA0_RLCT) != 0x0)
|
||||
;
|
||||
|
||||
/* Init register to match PCM expectation */
|
||||
write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF);
|
||||
write32(&mtk_spm->spm_bus_protect2_mask_b, SPM_BUS_PROTECT2_MASK_B_DEF);
|
||||
write32(&mtk_spm->pcm_reg_data_ini, 0);
|
||||
|
||||
spm_set_pcm_flags(pwrctrl);
|
||||
|
||||
/* Kick PCM to run (only toggle PCM_KICK) */
|
||||
setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
|
||||
|
||||
/* Reset md32pcm */
|
||||
SET32_BITFIELDS((void *)MD32PCM_CFGREG_SW_RSTN,
|
||||
MD32PCM_CFGREG_SW_RSTN_RESET, 1);
|
||||
|
||||
/* Waiting for SPM init done */
|
||||
udelay(SPM_INIT_DONE_US);
|
||||
}
|
||||
|
||||
static void reset_spm(struct mtk_mcu *mcu)
|
||||
{
|
||||
struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)mcu->priv;
|
||||
|
||||
spm_parse_firmware(mcu);
|
||||
spm_reset_and_init_pcm();
|
||||
spm_kick_im_to_fetch(pcm);
|
||||
spm_init_pcm_register();
|
||||
spm_set_wakeup_event(&spm_init_ctrl);
|
||||
spm_kick_pcm_to_run(&spm_init_ctrl);
|
||||
}
|
||||
|
||||
static struct mtk_mcu spm = {
|
||||
.firmware_name = CONFIG_SPM_FIRMWARE,
|
||||
.reset = reset_spm,
|
||||
};
|
||||
|
||||
int spm_init(void)
|
||||
{
|
||||
struct dyna_load_pcm pcm;
|
||||
struct stopwatch sw;
|
||||
|
||||
stopwatch_init(&sw);
|
||||
|
||||
spm_register_init();
|
||||
spm_set_power_control(&spm_init_ctrl);
|
||||
spm_set_sysclk_settle();
|
||||
spm_extern_initialize();
|
||||
|
||||
spm.load_buffer = _dram_dma;
|
||||
spm.buffer_size = REGION_SIZE(dram_dma);
|
||||
spm.priv = (void *)&pcm;
|
||||
|
||||
if (mtk_init_mcu(&spm)) {
|
||||
printk(BIOS_ERR, "SPM: %s: failed in mtk_init_mcu\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "SPM: %s done in %ld msecs, spm pc = %#x\n",
|
||||
__func__, stopwatch_duration_msecs(&sw),
|
||||
read32(&mtk_spm->md32pcm_pc));
|
||||
|
||||
return 0;
|
||||
return &spm_init_ctrl;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,8 +3,10 @@
|
|||
#ifndef SOC_MEDIATEK_MT8192_SPM_H
|
||||
#define SOC_MEDIATEK_MT8192_SPM_H
|
||||
|
||||
#include <device/mmio.h>
|
||||
#include <soc/addressmap.h>
|
||||
#include <soc/mtcmos.h>
|
||||
#include <soc/spm_common.h>
|
||||
#include <types.h>
|
||||
|
||||
/* SPM READ/WRITE CFG */
|
||||
|
|
@ -51,7 +53,7 @@
|
|||
#define SYS_TIMER_START_EN_LSB (1U << 0) /* 1b */
|
||||
|
||||
/* MD32PCM_CFGREG_SW_RSTN (0x10006000+0xA00) */
|
||||
#define MD32PCM_CFGREG_SW_RSTN_RESET (1U << 0) /* 1b */
|
||||
DEFINE_BIT(MD32PCM_CFGREG_SW_RSTN_RESET, 0)
|
||||
|
||||
/**************************************
|
||||
* Config and Parameter
|
||||
|
|
@ -660,20 +662,6 @@ check_member(mtk_spm_regs, md32pcm_dma0_rlct, 0xc24);
|
|||
|
||||
static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;
|
||||
|
||||
struct pcm_desc {
|
||||
u32 pmem_words;
|
||||
u32 total_words;
|
||||
u32 pmem_start;
|
||||
u32 dmem_start;
|
||||
};
|
||||
|
||||
struct dyna_load_pcm {
|
||||
u8 *buf; /* binary array */
|
||||
struct pcm_desc desc;
|
||||
};
|
||||
|
||||
int spm_init(void);
|
||||
|
||||
static const struct power_domain_data disp[] = {
|
||||
{
|
||||
.pwr_con = &mtk_spm->dis_pwr_con,
|
||||
|
|
|
|||
|
|
@ -1,16 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <assert.h>
|
||||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
#include <device/mmio.h>
|
||||
#include <soc/mcu_common.h>
|
||||
#include <soc/spm.h>
|
||||
#include <soc/spm_common.h>
|
||||
#include <soc/symbols.h>
|
||||
#include <timer.h>
|
||||
|
||||
#define SPM_SYSTEM_BASE_OFFSET 0x40000000
|
||||
|
||||
static const struct pwr_ctrl spm_init_ctrl = {
|
||||
/* Auto-gen Start */
|
||||
|
|
@ -127,7 +119,7 @@ static const struct pwr_ctrl spm_init_ctrl = {
|
|||
/* Auto-gen End */
|
||||
};
|
||||
|
||||
static void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
|
||||
void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
|
||||
{
|
||||
/* Auto-gen Start */
|
||||
|
||||
|
|
@ -307,7 +299,7 @@ static void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
|
|||
/* Auto-gen End */
|
||||
}
|
||||
|
||||
static void spm_register_init(void)
|
||||
void spm_register_init(void)
|
||||
{
|
||||
/* Enable register control */
|
||||
write32(&mtk_spm->poweron_config_set,
|
||||
|
|
@ -372,24 +364,7 @@ static void spm_register_init(void)
|
|||
SPM_ACK_CHK_3_CON_CLR_ALL);
|
||||
}
|
||||
|
||||
static void spm_set_sysclk_settle(void)
|
||||
{
|
||||
write32(&mtk_spm->spm_clk_settle, SPM_SYSCLK_SETTLE);
|
||||
}
|
||||
|
||||
static void spm_code_swapping(void)
|
||||
{
|
||||
u32 mask;
|
||||
|
||||
mask = read32(&mtk_spm->spm_wakeup_event_mask);
|
||||
write32(&mtk_spm->spm_wakeup_event_mask,
|
||||
mask & ~SPM_WAKEUP_EVENT_MASK_BIT0);
|
||||
write32(&mtk_spm->spm_cpu_wakeup_event, 1);
|
||||
write32(&mtk_spm->spm_cpu_wakeup_event, 0);
|
||||
write32(&mtk_spm->spm_wakeup_event_mask, mask);
|
||||
}
|
||||
|
||||
static void spm_reset_and_init_pcm(void)
|
||||
void spm_reset_and_init_pcm(void)
|
||||
{
|
||||
bool first_load_fw = true;
|
||||
|
||||
|
|
@ -424,58 +399,7 @@ static void spm_reset_and_init_pcm(void)
|
|||
REG_MD32_APB_INTERNAL_EN_LSB);
|
||||
}
|
||||
|
||||
static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm)
|
||||
{
|
||||
uintptr_t ptr;
|
||||
u32 dmem_words;
|
||||
u32 pmem_words;
|
||||
u32 total_words;
|
||||
u32 pmem_start;
|
||||
u32 dmem_start;
|
||||
|
||||
ptr = (uintptr_t)pcm->buf + SPM_SYSTEM_BASE_OFFSET;
|
||||
pmem_words = pcm->desc.pmem_words;
|
||||
total_words = pcm->desc.total_words;
|
||||
dmem_words = total_words - pmem_words;
|
||||
pmem_start = pcm->desc.pmem_start;
|
||||
dmem_start = pcm->desc.dmem_start;
|
||||
|
||||
printk(BIOS_DEBUG, "%s: ptr = %#lx, pmem/dmem words = %#x/%#x\n",
|
||||
__func__, (long)ptr, pmem_words, dmem_words);
|
||||
|
||||
/* DMA needs 16-byte aligned source data. */
|
||||
assert(ptr % 16 == 0);
|
||||
/* Program/Data must also be 16-byte (4-word) aligned. */
|
||||
assert(pmem_words % 4 == 0);
|
||||
assert(dmem_words % 4 == 0);
|
||||
|
||||
write32(&mtk_spm->md32pcm_dma0_src, ptr);
|
||||
write32(&mtk_spm->md32pcm_dma0_dst, pmem_start);
|
||||
write32(&mtk_spm->md32pcm_dma0_wppt, pmem_words);
|
||||
write32(&mtk_spm->md32pcm_dma0_wpto, dmem_start);
|
||||
write32(&mtk_spm->md32pcm_dma0_count, total_words);
|
||||
write32(&mtk_spm->md32pcm_dma0_con, MD32PCM_DMA0_CON_VAL);
|
||||
write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL);
|
||||
|
||||
setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
|
||||
}
|
||||
|
||||
static void spm_init_pcm_register(void)
|
||||
{
|
||||
/* Init r0 with POWER_ON_VAL0 */
|
||||
write32(&mtk_spm->pcm_reg_data_ini,
|
||||
read32(&mtk_spm->spm_power_on_val0));
|
||||
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0);
|
||||
write32(&mtk_spm->pcm_pwr_io_en, 0);
|
||||
|
||||
/* Init r7 with POWER_ON_VAL1 */
|
||||
write32(&mtk_spm->pcm_reg_data_ini,
|
||||
read32(&mtk_spm->spm_power_on_val1));
|
||||
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
|
||||
write32(&mtk_spm->pcm_pwr_io_en, 0);
|
||||
}
|
||||
|
||||
static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
|
||||
void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
|
||||
{
|
||||
u32 val, mask;
|
||||
|
||||
|
|
@ -519,91 +443,7 @@ static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
|
|||
clrbits32(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB);
|
||||
}
|
||||
|
||||
static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl)
|
||||
const struct pwr_ctrl *get_pwr_ctrl(void)
|
||||
{
|
||||
u32 pcm_flags = pwrctrl->pcm_flags, pcm_flags1 = pwrctrl->pcm_flags1;
|
||||
|
||||
/* Set PCM flags and data */
|
||||
if (pwrctrl->pcm_flags_cust_clr != 0)
|
||||
pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
|
||||
if (pwrctrl->pcm_flags_cust_set != 0)
|
||||
pcm_flags |= pwrctrl->pcm_flags_cust_set;
|
||||
if (pwrctrl->pcm_flags1_cust_clr != 0)
|
||||
pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
|
||||
if (pwrctrl->pcm_flags1_cust_set != 0)
|
||||
pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
|
||||
|
||||
write32(&mtk_spm->spm_sw_flag_0, pcm_flags);
|
||||
write32(&mtk_spm->spm_sw_flag_1, pcm_flags1);
|
||||
write32(&mtk_spm->spm_sw_rsv_7, pcm_flags);
|
||||
write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1);
|
||||
}
|
||||
|
||||
static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl)
|
||||
{
|
||||
/* Waiting for loading SPMFW done*/
|
||||
while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0)
|
||||
;
|
||||
|
||||
/* Init register to match PCM expectation */
|
||||
write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF);
|
||||
write32(&mtk_spm->spm_bus_protect2_mask_b,
|
||||
SPM_BUS_PROTECT2_MASK_B_DEF);
|
||||
write32(&mtk_spm->pcm_reg_data_ini, 0);
|
||||
|
||||
spm_set_pcm_flags(pwrctrl);
|
||||
|
||||
/* Kick PCM to run (only toggle PCM_KICK) */
|
||||
setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
|
||||
|
||||
/* Reset md32pcm */
|
||||
setbits32(&mtk_spm->md32pcm_cfgreg_sw_rstn,
|
||||
MD32PCM_CFGREG_SW_RSTN_RESET);
|
||||
|
||||
/* Waiting for SPM init done */
|
||||
udelay(SPM_INIT_DONE_US);
|
||||
}
|
||||
|
||||
static void reset_spm(struct mtk_mcu *mcu)
|
||||
{
|
||||
struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)mcu->priv;
|
||||
|
||||
spm_parse_firmware(mcu);
|
||||
spm_reset_and_init_pcm();
|
||||
spm_kick_im_to_fetch(pcm);
|
||||
spm_init_pcm_register();
|
||||
spm_set_wakeup_event(&spm_init_ctrl);
|
||||
spm_kick_pcm_to_run(&spm_init_ctrl);
|
||||
}
|
||||
|
||||
static struct mtk_mcu spm = {
|
||||
.firmware_name = CONFIG_SPM_FIRMWARE,
|
||||
.reset = reset_spm,
|
||||
};
|
||||
|
||||
int spm_init(void)
|
||||
{
|
||||
struct dyna_load_pcm pcm;
|
||||
struct stopwatch sw;
|
||||
|
||||
stopwatch_init(&sw);
|
||||
|
||||
spm_register_init();
|
||||
spm_set_power_control(&spm_init_ctrl);
|
||||
spm_set_sysclk_settle();
|
||||
|
||||
spm.load_buffer = _dram_dma;
|
||||
spm.buffer_size = REGION_SIZE(dram_dma);
|
||||
spm.priv = (void *)&pcm;
|
||||
|
||||
if (mtk_init_mcu(&spm)) {
|
||||
printk(BIOS_ERR, "SPM: %s: failed in mtk_init_mcu\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "SPM: %s done in %ld msecs, spm pc = %#x\n",
|
||||
__func__, stopwatch_duration_msecs(&sw),
|
||||
read32(&mtk_spm->md32pcm_pc));
|
||||
|
||||
return 0;
|
||||
return &spm_init_ctrl;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
#include <device/mmio.h>
|
||||
#include <soc/addressmap.h>
|
||||
#include <soc/mtcmos.h>
|
||||
#include <soc/spm_common.h>
|
||||
#include <types.h>
|
||||
|
||||
/* SPM READ/WRITE CFG */
|
||||
|
|
@ -952,20 +953,6 @@ check_member(mtk_spm_regs, ulposc_con, 0x644);
|
|||
|
||||
static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;
|
||||
|
||||
struct pcm_desc {
|
||||
u32 pmem_words;
|
||||
u32 total_words;
|
||||
u32 pmem_start;
|
||||
u32 dmem_start;
|
||||
};
|
||||
|
||||
struct dyna_load_pcm {
|
||||
u8 *buf; /* binary array */
|
||||
struct pcm_desc desc;
|
||||
};
|
||||
|
||||
int spm_init(void);
|
||||
|
||||
static const struct power_domain_data disp[] = {
|
||||
{
|
||||
.pwr_con = &mtk_spm->vppsys0_pwr_con,
|
||||
|
|
|
|||
|
|
@ -1,16 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <assert.h>
|
||||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
#include <device/mmio.h>
|
||||
#include <soc/mcu_common.h>
|
||||
#include <soc/spm.h>
|
||||
#include <soc/spm_common.h>
|
||||
#include <soc/symbols.h>
|
||||
#include <timer.h>
|
||||
|
||||
#define SPM_SYSTEM_BASE_OFFSET 0x40000000
|
||||
|
||||
static const struct pwr_ctrl spm_init_ctrl = {
|
||||
.pcm_flags = SPM_FLAG_DISABLE_VCORE_DVS | SPM_FLAG_DISABLE_VCORE_DFS |
|
||||
|
|
@ -284,7 +276,7 @@ static const struct pwr_ctrl spm_init_ctrl = {
|
|||
.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
|
||||
};
|
||||
|
||||
static void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
|
||||
void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
|
||||
{
|
||||
/* Auto-gen Start */
|
||||
|
||||
|
|
@ -423,7 +415,7 @@ static void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
|
|||
/* Auto-gen End */
|
||||
}
|
||||
|
||||
static void spm_register_init(void)
|
||||
void spm_register_init(void)
|
||||
{
|
||||
/* Enable register control */
|
||||
write32(&mtk_spm->poweron_config_set,
|
||||
|
|
@ -478,24 +470,7 @@ static void spm_register_init(void)
|
|||
|
||||
}
|
||||
|
||||
static void spm_set_sysclk_settle(void)
|
||||
{
|
||||
write32(&mtk_spm->spm_clk_settle, SPM_SYSCLK_SETTLE);
|
||||
}
|
||||
|
||||
static void spm_code_swapping(void)
|
||||
{
|
||||
u32 mask;
|
||||
|
||||
mask = read32(&mtk_spm->spm_wakeup_event_mask);
|
||||
write32(&mtk_spm->spm_wakeup_event_mask,
|
||||
mask & ~SPM_WAKEUP_EVENT_MASK_BIT0);
|
||||
write32(&mtk_spm->spm_cpu_wakeup_event, 1);
|
||||
write32(&mtk_spm->spm_cpu_wakeup_event, 0);
|
||||
write32(&mtk_spm->spm_wakeup_event_mask, mask);
|
||||
}
|
||||
|
||||
static void spm_reset_and_init_pcm(void)
|
||||
void spm_reset_and_init_pcm(void)
|
||||
{
|
||||
bool first_load_fw = true;
|
||||
|
||||
|
|
@ -530,55 +505,7 @@ static void spm_reset_and_init_pcm(void)
|
|||
REG_MD32_APB_INTERNAL_EN_LSB);
|
||||
}
|
||||
|
||||
static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm)
|
||||
{
|
||||
uintptr_t ptr;
|
||||
u32 dmem_words;
|
||||
u32 pmem_words;
|
||||
u32 total_words;
|
||||
u32 pmem_start;
|
||||
u32 dmem_start;
|
||||
|
||||
ptr = (uintptr_t)pcm->buf + SPM_SYSTEM_BASE_OFFSET;
|
||||
pmem_words = pcm->desc.pmem_words;
|
||||
total_words = pcm->desc.total_words;
|
||||
dmem_words = total_words - pmem_words;
|
||||
pmem_start = pcm->desc.pmem_start;
|
||||
dmem_start = pcm->desc.dmem_start;
|
||||
|
||||
printk(BIOS_DEBUG, "%s: ptr = %#lx, pmem/dmem words = %#x/%#x\n",
|
||||
__func__, (long)ptr, pmem_words, dmem_words);
|
||||
|
||||
/* DMA needs 16-byte aligned source data. */
|
||||
assert(ptr % 16 == 0);
|
||||
|
||||
write32(&mtk_spm->md32pcm_dma0_src, ptr);
|
||||
write32(&mtk_spm->md32pcm_dma0_dst, pmem_start);
|
||||
write32(&mtk_spm->md32pcm_dma0_wppt, pmem_words);
|
||||
write32(&mtk_spm->md32pcm_dma0_wpto, dmem_start);
|
||||
write32(&mtk_spm->md32pcm_dma0_count, total_words);
|
||||
write32(&mtk_spm->md32pcm_dma0_con, MD32PCM_DMA0_CON_VAL);
|
||||
write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL);
|
||||
|
||||
setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
|
||||
}
|
||||
|
||||
static void spm_init_pcm_register(void)
|
||||
{
|
||||
/* Init r0 with POWER_ON_VAL0 */
|
||||
write32(&mtk_spm->pcm_reg_data_ini,
|
||||
read32(&mtk_spm->spm_power_on_val0));
|
||||
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0);
|
||||
write32(&mtk_spm->pcm_pwr_io_en, 0);
|
||||
|
||||
/* Init r7 with POWER_ON_VAL1 */
|
||||
write32(&mtk_spm->pcm_reg_data_ini,
|
||||
read32(&mtk_spm->spm_power_on_val1));
|
||||
write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
|
||||
write32(&mtk_spm->pcm_pwr_io_en, 0);
|
||||
}
|
||||
|
||||
static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
|
||||
void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
|
||||
{
|
||||
u32 val, mask;
|
||||
|
||||
|
|
@ -623,91 +550,7 @@ static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
|
|||
SYS_TIMER_START_EN_LSB, 0);
|
||||
}
|
||||
|
||||
static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl)
|
||||
const struct pwr_ctrl *get_pwr_ctrl(void)
|
||||
{
|
||||
u32 pcm_flags = pwrctrl->pcm_flags, pcm_flags1 = pwrctrl->pcm_flags1;
|
||||
|
||||
/* Set PCM flags and data */
|
||||
if (pwrctrl->pcm_flags_cust_clr != 0)
|
||||
pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
|
||||
if (pwrctrl->pcm_flags_cust_set != 0)
|
||||
pcm_flags |= pwrctrl->pcm_flags_cust_set;
|
||||
if (pwrctrl->pcm_flags1_cust_clr != 0)
|
||||
pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
|
||||
if (pwrctrl->pcm_flags1_cust_set != 0)
|
||||
pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
|
||||
|
||||
write32(&mtk_spm->spm_sw_flag_0, pcm_flags);
|
||||
write32(&mtk_spm->spm_sw_flag_1, pcm_flags1);
|
||||
write32(&mtk_spm->spm_sw_rsv_7, pcm_flags);
|
||||
write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1);
|
||||
}
|
||||
|
||||
static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl)
|
||||
{
|
||||
/* Waiting for loading SPMFW done*/
|
||||
while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0)
|
||||
;
|
||||
|
||||
/* Init register to match PCM expectation */
|
||||
write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF);
|
||||
write32(&mtk_spm->spm_bus_protect2_mask_b,
|
||||
SPM_BUS_PROTECT2_MASK_B_DEF);
|
||||
write32(&mtk_spm->pcm_reg_data_ini, 0);
|
||||
|
||||
spm_set_pcm_flags(pwrctrl);
|
||||
|
||||
/* Kick PCM to run (only toggle PCM_KICK) */
|
||||
setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
|
||||
|
||||
/* Reset md32pcm */
|
||||
SET32_BITFIELDS(&mtk_spm->md32pcm_cfgreg_sw_rstn,
|
||||
MD32PCM_CFGREG_SW_RSTN_RESET, 1);
|
||||
|
||||
/* Waiting for SPM init done */
|
||||
udelay(SPM_INIT_DONE_US);
|
||||
}
|
||||
|
||||
static void reset_spm(struct mtk_mcu *mcu)
|
||||
{
|
||||
struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)mcu->priv;
|
||||
|
||||
spm_parse_firmware(mcu);
|
||||
spm_reset_and_init_pcm();
|
||||
spm_kick_im_to_fetch(pcm);
|
||||
spm_init_pcm_register();
|
||||
spm_set_wakeup_event(&spm_init_ctrl);
|
||||
spm_kick_pcm_to_run(&spm_init_ctrl);
|
||||
}
|
||||
|
||||
static struct mtk_mcu spm = {
|
||||
.firmware_name = CONFIG_SPM_FIRMWARE,
|
||||
.reset = reset_spm,
|
||||
};
|
||||
|
||||
int spm_init(void)
|
||||
{
|
||||
struct dyna_load_pcm pcm;
|
||||
struct stopwatch sw;
|
||||
|
||||
stopwatch_init(&sw);
|
||||
|
||||
spm_register_init();
|
||||
spm_set_power_control(&spm_init_ctrl);
|
||||
spm_set_sysclk_settle();
|
||||
|
||||
spm.load_buffer = _dram_dma;
|
||||
spm.buffer_size = REGION_SIZE(dram_dma);
|
||||
spm.priv = (void *)&pcm;
|
||||
|
||||
if (mtk_init_mcu(&spm)) {
|
||||
printk(BIOS_ERR, "SPM: %s: failed in mtk_init_mcu\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "SPM: %s done in %ld msecs, spm pc = %#x\n",
|
||||
__func__, stopwatch_duration_msecs(&sw),
|
||||
read32(&mtk_spm->md32pcm_pc));
|
||||
|
||||
return 0;
|
||||
return &spm_init_ctrl;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue