soc/intel/icelake: Skip FSP-S IGD related UPD override
Default FSP values for "GtFreqMax" and "CdClock" UPDs are "Auto", hence related FSP-S UPD override can be avoided from coreboot. As per FSP-S UPD Header (FspsUpd.h) /** Offset 0x020E - GT Frequency Limit 0xFF: Auto(Default) **/ UINT8 GtFreqMax; /** Offset 0x0209 - CdClock Frequency selection 0: (Default) Auto **/ UINT8 CdClock; TEST=Able to get Pre-OS display on ICLRVP and Dragonegg platform. Change-Id: Ie500dd5fad5cd358ea3fad4d5c0be1b0c148584b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
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@ -96,10 +96,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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params->PeiGraphicsPeimInit = 1;
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else
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params->PeiGraphicsPeimInit = 0;
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if (dev && dev->enabled) {
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params->GtFreqMax = 2;
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params->CdClock = 3;
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}
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/* Unlock upper 8 bytes of RTC RAM */
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params->PchLockDownRtcMemoryLock = 0;
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