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soc/intel/icelake: Skip FSP-S IGD related UPD override 

Default FSP values for "GtFreqMax" and "CdClock" UPDs are "Auto", hence
related FSP-S UPD override can be avoided from coreboot.

As per FSP-S UPD Header (FspsUpd.h)

/** Offset 0x020E - GT Frequency Limit
  0xFF: Auto(Default)
**/
UINT8 GtFreqMax;

/** Offset 0x0209 - CdClock Frequency selection
  0: (Default) Auto
**/
UINT8 CdClock;

TEST=Able to get Pre-OS display on ICLRVP and Dragonegg platform.

Change-Id: Ie500dd5fad5cd358ea3fad4d5c0be1b0c148584b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
This commit is contained in:
Subrata Banik 2020-02-19 19:09:06 +05:30 committed by Patrick Georgi
parent f07d3b4585
commit 9d667906f3
1 changed files with 0 additions and 4 deletions
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4
src/soc/intel/icelake/fsp_params.c
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@ -96,10 +96,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PeiGraphicsPeimInit = 1; params->PeiGraphicsPeimInit = 1;
else else
params->PeiGraphicsPeimInit = 0; params->PeiGraphicsPeimInit = 0;
if (dev && dev->enabled) {
params->GtFreqMax = 2;
params->CdClock = 3;
}
/* Unlock upper 8 bytes of RTC RAM */ /* Unlock upper 8 bytes of RTC RAM */
params->PchLockDownRtcMemoryLock = 0; params->PchLockDownRtcMemoryLock = 0;