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nb/intel/haswell/acpi: Update to ASL 2.0 syntax 

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: Ibcc54c2332945fff28d6502edb7eefa06f764bdd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43152
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-07-06 22:27:39 +02:00 committed by Patrick Georgi
parent 05f996d433
commit 9d69d881e6
1 changed files with 4 additions and 4 deletions
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8
src/northbridge/intel/haswell/acpi/hostbridge.asl
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@ -88,7 +88,7 @@ Device (MCHC)
Name (CTCU, 2) /* CTDP Up Select */
Name (SPL1, 0) /* Saved PL1 value */
OperationRegion (MCHB, SystemMemory, Add(DEFAULT_MCHBAR,0x5000), 0x1000)
OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR + 0x5000, 0x1000)
Field (MCHB, DWordAcc, Lock, Preserve)
{
Offset (0x930), /* PACKAGE_POWER_SKU */
@ -140,7 +140,7 @@ Device (MCHC)
External (\_SB.CP00._PSS)
Method (PSSS, 1, NotSerialized)
{
Local0 = One /* Start at P1 */
Local0 = 1 /* Start at P1 */
Local1 = SizeOf (\_SB.CP00._PSS)
While (Local0 < Local1) {
@ -252,7 +252,7 @@ Device (MCHC)
Return (0)
}
Store ("Enable PL1 Limit", Debug)
Debug = "Enable PL1 Limit"
/* Set _PPC to LFM */
Local0 = PSSS (LFM_)
@ -280,7 +280,7 @@ Device (MCHC)
Return (0)
}
Store ("Disable PL1 Limit", Debug)
Debug = "Disable PL1 Limit"
/* Clear PL1 CLAMP bit */
PL1C = 0