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soc/amd/stoneyridge: Fix device IDs 

Update pci_devs.h to the correct IDs for Stoney Ridge.

BUG=chrome-os-partner:62578372

Change-Id: Ic1a7fe8d95c34b80e21cc089168732372d9690a3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20200
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson 2017-06-26 11:21:47 -06:00 committed by Martin Roth
parent 89bb6ab40a
commit 9d6b8b4d68
1 changed files with 11 additions and 11 deletions
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22
src/soc/amd/stoneyridge/include/soc/pci_devs.h
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@ -21,7 +21,7 @@
/* XHCI */ /* XHCI */
#define XHCI_DEV 0x10 #define XHCI_DEV 0x10
#define XHCI_FUNC 0 #define XHCI_FUNC 0
#define XHCI_DEVID 0x7814 #define XHCI_DEVID 0x7914
#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC) #define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC)
#define XHCI2_DEV 0x10 #define XHCI2_DEV 0x10
@ -32,9 +32,9 @@
/* SATA */ /* SATA */
#define SATA_DEV 0x11 #define SATA_DEV 0x11
#define SATA_FUNC 0 #define SATA_FUNC 0
#define SATA_IDE_DEVID 0x7800 #define SATA_IDE_DEVID 0x7900
#define AHCI_DEVID_MS 0x7801 #define AHCI_DEVID_MS 0x7901
#define AHCI_DEVID_AMD 0x7804 #define AHCI_DEVID_AMD 0x7904
#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) #define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC)
/* OHCI */ /* OHCI */
@ -53,13 +53,13 @@
#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC) #define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC)
/* EHCI */ /* EHCI */
#define EHCI1_DEV 0x12 #define EHCI_DEV 0x12
#define EHCI1_FUNC 2 #define EHCI_FUNC 0
#define EHCI2_DEV 0x13 #define EHCI2_DEV 0x13
#define EHCI2_FUNC 2 #define EHCI2_FUNC 2
#define EHCI3_DEV 0x16 #define EHCI3_DEV 0x16
#define EHCI3_FUNC 2 #define EHCI3_FUNC 2
#define EHCI_DEVID 0x7808 #define EHCI_DEVID 0x7908
#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC) #define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC)
#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC) #define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC)
#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC) #define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC)
@ -67,7 +67,7 @@
/* SMBUS */ /* SMBUS */
#define SMBUS_DEV 0x14 #define SMBUS_DEV 0x14
#define SMBUS_FUNC 0 #define SMBUS_FUNC 0
#define SMBUS_DEVID 0x780b #define SMBUS_DEVID 0x790b
#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
/* IDE */ /* IDE */
@ -87,13 +87,13 @@
/* LPC BUS */ /* LPC BUS */
#define PCU_DEV 0x14 #define PCU_DEV 0x14
#define LPC_FUNC 3 #define LPC_FUNC 3
#define LPC_DEVID 0x780e #define LPC_DEVID 0x790e
#define LPC_DEVFN PCI_DEVFN(LPC_DEV, LPC_FUNC) #define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC)
/* SD Controller */ /* SD Controller */
#define SD_DEV 0x14 #define SD_DEV 0x14
#define SD_FUNC 7 #define SD_FUNC 7
#define SD_DEVID 0x7806 #define SD_DEVID 0x7906
#define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) #define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC)
/* PCIe Ports */ /* PCIe Ports */