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src/cpu: Get rid of whitespace before tab 

Change-Id: Ic501f5f9e8cd79774eb2a8d8902f01853d746470
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2018-05-28 15:41:12 +02:00 committed by Patrick Georgi
parent 0d8f1dac9e
commit 9d75957116
4 changed files with 23 additions and 23 deletions
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2
src/cpu/allwinner/a10/twi.h
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@ -31,7 +31,7 @@
/* TWI_STAT values */ /* TWI_STAT values */
enum twi_status { enum twi_status {
TWI_STAT_BUS_ERROR = 0x00, /**< Bus error */ TWI_STAT_BUS_ERROR = 0x00, /**< Bus error */
TWI_STAT_TX_START = 0x08, /**< START sent */ TWI_STAT_TX_START = 0x08, /**< START sent */
TWI_STAT_TX_RSTART = 0x10, /**< Repeated START sent */ TWI_STAT_TX_RSTART = 0x10, /**< Repeated START sent */
TWI_STAT_TX_AW_ACK = 0x18, /**< Sent address+read, ACK */ TWI_STAT_TX_AW_ACK = 0x18, /**< Sent address+read, ACK */

36
src/cpu/amd/family_10h-family_15h/defaults.h
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@ -523,7 +523,7 @@ static const struct {
/* Errata 281 Workaround */ /* Errata 281 Workaround */
{ 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1), { 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1),
AMD_PTYPE_SVR, 0x00000001, 0x0000000F }, AMD_PTYPE_SVR, 0x00000001, 0x0000000F },
/* [3:0] RspTok = 0001b */ /* [3:0] RspTok = 0001b */
{ 3, 0x144, AMD_FAM15_ALL, AMD_PTYPE_ALL, { 3, 0x144, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000028, 0x000000ff }, 0x00000028, 0x000000ff },
@ -758,7 +758,7 @@ static const struct {
0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ 0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
{ 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ 0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
/* Link Phy Receiver Loop Filter Registers */ /* Link Phy Receiver Loop Filter Registers */
{ 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
@ -782,28 +782,28 @@ static const struct {
[20:16] RttIndex = 04h */ [20:16] RttIndex = 04h */
{ 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa, 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa,
P0XmtRdPtr = 0x2 P0XmtRdPtr = 0x2
P1RcvRdPtr = 0xa P1RcvRdPtr = 0xa
P1XmtRdPtr = 0x0 */ P1XmtRdPtr = 0x0 */
{ 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa, 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa,
P0XmtRdPtr = 0x2 P0XmtRdPtr = 0x2
P1RcvRdPtr = 0xa P1RcvRdPtr = 0xa
P1XmtRdPtr = 0x0 */ P1XmtRdPtr = 0x0 */
{ 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd, 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd,
P0XmtRdPtr = 0x4 P0XmtRdPtr = 0x4
P1RcvRdPtr = 0xd P1RcvRdPtr = 0xd
P1XmtRdPtr = 0x0 */ P1XmtRdPtr = 0x0 */
{ 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd, 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd,
P0XmtRdPtr = 0x4 P0XmtRdPtr = 0x4
P1RcvRdPtr = 0xd P1RcvRdPtr = 0xd
P1XmtRdPtr = 0x0 */ P1XmtRdPtr = 0x0 */
/* Link Phy Receiver Loop Filter Registers */ /* Link Phy Receiver Loop Filter Registers */
{ 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, { 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,

6
src/cpu/amd/microcode/microcode.c
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@ -30,9 +30,9 @@
#define UCODE_SECTION_START_ID 0x00000001 #define UCODE_SECTION_START_ID 0x00000001
#define UCODE_MAGIC 0x00414d44 #define UCODE_MAGIC 0x00414d44
#define F1XH_MPB_MAX_SIZE 2048 #define F1XH_MPB_MAX_SIZE 2048
#define F15H_MPB_MAX_SIZE 4096 #define F15H_MPB_MAX_SIZE 4096
#define CONT_HDR 12 #define CONT_HDR 12
#define SECT_HDR 8 #define SECT_HDR 8
/* /*

2
src/cpu/x86/smm/smmrelocate.S
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@ -67,7 +67,7 @@
* *
* Example (with SMM handler living at 0xa0000): * Example (with SMM handler living at 0xa0000):
* *
* LAPICID SMBASE SMM Entry SAVE STATE * LAPICID SMBASE SMM Entry SAVE STATE
* 0 0xa0000 0xa8000 0xafd00 * 0 0xa0000 0xa8000 0xafd00
* 1 0x9fc00 0xa7c00 0xaf900 * 1 0x9fc00 0xa7c00 0xaf900
* 2 0x9f800 0xa7800 0xaf500 * 2 0x9f800 0xa7800 0xaf500