soc/intel/common: provide default tis_plat_irq_status() implementation
On Intel platforms utilizing the CR50 TPM the interrupts are routed to GPIOs connected to the GPE blocks. Therefore, provide a common implementation for tis_plat_irq_status() to reduce code duplication. This code could be further extended to not be added based on MAINBOARD_HAS_TPM_CR50, but that's all that's using it for now. Change-Id: I955df0a536408b2ccd07146893337c53799e243f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19369 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
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@ -130,4 +130,10 @@ config SOC_INTEL_COMMON_NHLT
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bool
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default n
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config TPM_TIS_ACPI_INTERRUPT
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int
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help
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acpi_get_gpe() is used to provide interrupt status to TPM layer.
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This option specifies the GPE number.
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endif # SOC_INTEL_COMMON
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@ -37,6 +37,11 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c
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smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c
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bootblock-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c
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verstage-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c
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romstage-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c
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ramstage-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c
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# Create and add the MRC cache to the cbfs image
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ifneq ($(CONFIG_CHROMEOS),y)
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$(obj)/mrc.cache: $(obj)/config.h
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@ -0,0 +1,22 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2017 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <tpm.h>
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int tis_plat_irq_status(void)
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{
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return acpi_get_gpe(CONFIG_TPM_TIS_ACPI_INTERRUPT);
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}
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