mb/google/guybrush/var/nipperkin: Add ALC5682I and MAX98360 support
Add ID "10029836" for machine driver, "RTL5682" for ALC5682I and "MX98357A" for MAX98360. BUG=b:198716348 TEST=Build nipperkin, codec is functional with new machine driver. Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: Iab9d11adb7cd08effa2a9b6a627832bd89cb3cb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS
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select DRIVERS_ACPI_THERMAL_ZONE
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select DRIVERS_ACPI_THERMAL_ZONE
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select DRIVERS_AMD_I2S_MACHINE_DEV
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select DRIVERS_AMD_I2S_MACHINE_DEV
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select DRIVERS_GENERIC_GPIO_KEYS
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select DRIVERS_GENERIC_GPIO_KEYS
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select DRIVERS_GENERIC_MAX98357A
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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select DRIVERS_I2C_HID
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select DRIVERS_PCIE_RTD3_DEVICE
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select DRIVERS_PCIE_RTD3_DEVICE
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@ -32,7 +32,14 @@ end
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chip soc/amd/cezanne
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chip soc/amd/cezanne
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device domain 0 on
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device domain 0 on
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device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
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device ref acp on
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chip drivers/amd/i2s_machine_dev
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register "hid" = ""10029836""
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device generic 0.0 on end
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end
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end # Audio
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end
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end # domain
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end # domain
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register "slow_ppt_limit_mW" = "25000"
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register "slow_ppt_limit_mW" = "25000"
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@ -101,7 +108,7 @@ chip soc/amd/cezanne
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device ref i2c_2 on
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device ref i2c_2 on
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chip drivers/i2c/generic
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "hid" = ""RTL5682""
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register "name" = ""RT58""
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register "name" = ""RT58""
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register "desc" = ""Realtek RT5682""
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register "desc" = ""Realtek RT5682""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_90)"
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_90)"
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@ -128,4 +135,11 @@ chip soc/amd/cezanne
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end
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end
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end
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end
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chip drivers/generic/max98357a
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register "hid" = ""MX98357A""
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register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_31)"
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register "sdmode_delay" = "5"
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device generic 0.1 on end
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end
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end # chip soc/amd/cezanne
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end # chip soc/amd/cezanne
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