diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index d4c4be8a29..0561d747f2 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -206,6 +206,9 @@ config HEAP_SIZE
 	hex
 	default 0x10000
 
+config GFX_GMA_DEFAULT_MMIO
+	default 0xfa000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT
+
 # Intel recommends reserving the following resources per PCIe TBT root port,
 # from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5
 # - 42 buses
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 18429b8236..5173b1cf03 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -674,6 +674,11 @@ struct soc_intel_alderlake_config {
 
 	/* i915 struct for GMA backlight control */
 	struct i915_gpu_controller_info gfx;
+
+	/*
+	 * IGD panel configuration
+	 */
+	struct i915_gpu_panel_config panel_cfg;
 };
 
 typedef struct soc_intel_alderlake_config config_t;
diff --git a/src/soc/intel/alderlake/romstage/Makefile.inc b/src/soc/intel/alderlake/romstage/Makefile.inc
index 99c1d2ca25..7f1a94b437 100644
--- a/src/soc/intel/alderlake/romstage/Makefile.inc
+++ b/src/soc/intel/alderlake/romstage/Makefile.inc
@@ -4,3 +4,4 @@ romstage-y += fsp_params.c
 romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-y += romstage.c
 romstage-y += systemagent.c
+romstage-$(CONFIG_EARLY_GFX_GMA) += graphics.c
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index b2d0120c7d..b34b55e638 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -423,6 +423,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	/* Override the memory init params through runtime debug capability */
 	if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE))
 		debug_override_memory_init_params(m_cfg);
+
+	if (CONFIG(HWBASE_STATIC_MMIO))
+		m_cfg->GttMmAdr = CONFIG_GFX_GMA_DEFAULT_MMIO;
 }
 
 __weak void mainboard_memory_init_params(FSPM_UPD *memupd)
diff --git a/src/soc/intel/alderlake/romstage/graphics.c b/src/soc/intel/alderlake/romstage/graphics.c
new file mode 100644
index 0000000000..4dd3b30731
--- /dev/null
+++ b/src/soc/intel/alderlake/romstage/graphics.c
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <drivers/intel/gma/i915_reg.h>
+#include <intelblocks/early_graphics.h>
+#include <soc/soc_chip.h>
+
+void early_graphics_soc_panel_init(void)
+{
+	const struct soc_intel_alderlake_config *soc_conf;
+	const struct i915_gpu_panel_config *panel_cfg;
+	void *mmio = (void *)CONFIG_GFX_GMA_DEFAULT_MMIO;
+	uint32_t reg32;
+	unsigned int pwm_period, pwm_polarity, pwm_duty;
+
+	soc_conf = config_of_soc();
+	panel_cfg = &soc_conf->panel_cfg;
+
+	reg32 = ((DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f) << 4;
+	reg32 |= PANEL_POWER_RESET;
+	write32(mmio + PCH_PP_CONTROL, reg32);
+
+	reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16;
+	reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff;
+	write32(mmio + PCH_PP_ON_DELAYS, reg32);
+
+	reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16;
+	reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff;
+	write32(mmio + PCH_PP_OFF_DELAYS, reg32);
+
+	if (!panel_cfg->backlight_pwm_hz)
+		return;
+
+	/* Configure backlight */
+	pwm_polarity = panel_cfg->backlight_polarity ? BXT_BLC_PWM_POLARITY : 0;
+	pwm_period = DIV_ROUND_CLOSEST(CONFIG_CPU_XTAL_HZ,
+				       panel_cfg->backlight_pwm_hz);
+	pwm_duty = DIV_ROUND_CLOSEST(pwm_period, 2); /* Start with 50 % */
+	write32(mmio + BXT_BLC_PWM_FREQ(0), pwm_period);
+	write32(mmio + BXT_BLC_PWM_CTL(0),  pwm_polarity);
+	write32(mmio + BXT_BLC_PWM_DUTY(0), pwm_duty);
+}