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tree/acpi: Replace constant "Zero" with actual number 

Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer 2022-12-26 09:43:07 +01:00
parent 42efd7f593
commit 9df60d36b2
40 changed files with 106 additions and 106 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/acpi/dsdt_top.asl
View File

@ -10,8 +10,8 @@
/* Operating system enumeration. */
Name (OSYS, 0)
/* Zero => PIC mode, 1 => APIC Mode */
Name (PICM, Zero)
/* 0 => PIC mode, 1 => APIC Mode */
Name (PICM, 0)
/* Power state (AC = 1) */
Name (PWRS, 1)

2
src/drivers/intel/gma/acpi/common.asl
View File

@ -6,7 +6,7 @@
Method(BRID, 1, NotSerialized)
{
Local0 = Match (BRIG, MEQ, Arg0, MTR, Zero, 2)
Local0 = Match (BRIG, MEQ, Arg0, MTR, 0, 2)
If (Local0 == Ones)
{
Return (SizeOf(BRIG) - 1)

6
src/drivers/intel/gma/acpi/configure_brightness_levels.asl
View File

@ -34,7 +34,7 @@
* Request back-light brightness change through mailbox 3
*
* @param Arg0 The brightness level to set in percent
* @Return Zero on success, Ones on failure
* @Return 0 on success, Ones on failure
* Errors: * ASLS is zero
* * Mailbox 3 support not advertised
* * Driver not loaded or not ready
@ -78,7 +78,7 @@
/* Request has been processed, check status: */
Local1 = (ASLC >> 12) & 3
If (Local1 == 0) {
Return (Zero)
Return (0)
} Else {
Return (Ones)
}
@ -114,7 +114,7 @@
/* Prevent DivideByZero if backlight control isn't enabled */
If (BCLM == 0)
{
Return (Zero)
Return (0)
}
/* Local0: current percentage */
Local0 = DRCL (BCLV * 100, BCLM)

2
src/northbridge/amd/pi/00730F01/acpi/northbridge.asl
View File

@ -10,7 +10,7 @@ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
Method(_BBN, 0, NotSerialized) /* Bus number = 0 */
{
Return(Zero)
Return(0)
}
Method(_STA, 0, NotSerialized)

2
src/soc/amd/cezanne/acpi/pci0.asl
View File

@ -6,7 +6,7 @@ Device(PCI0) {
External(TOM1, IntObj) /* Generated by root_complex.c */
Method(_BBN, 0, NotSerialized) {
Return(Zero) /* Bus number = 0 */
Return(0) /* Bus number = 0 */
}
Method(_STA, 0, NotSerialized) {

8
src/soc/amd/common/acpi/dptc.asl
View File

@ -11,7 +11,7 @@ Scope (\_SB)
/* If _SB.DDEF is not present, DPTC is not enabled so return early. */
If (!CondRefOf (\_SB.DDEF))
{
Return (Zero)
Return (0)
}
/* If _SB.DTHL is not present, then DPTC Tablet Mode is not enabled.
@ -21,14 +21,14 @@ Scope (\_SB)
(!\_SB.PCI0.LPCB.EC0.BTEX || \_SB.PCI0.LPCB.EC0.BFCR || \_SB.PCI0.LPCB.EC0.BFCT))
{
\_SB.DTHL()
Return (Zero)
Return (0)
}
/* If _SB.DTAB is not present, then DPTC Tablet Mode is not enabled. */
If (CondRefOf (\_SB.DTAB) && (\_SB.PCI0.LPCB.EC0.TBMD == 1))
{
\_SB.DTAB()
Return (Zero)
Return (0)
}
#if CONFIG(FEATURE_DYNAMIC_DPTC)
@ -36,6 +36,6 @@ Scope (\_SB)
#else
\_SB.DDEF()
#endif
Return (Zero)
Return (0)
}
}

2
src/soc/amd/glinda/acpi/pci0.asl
View File

@ -8,7 +8,7 @@ Device(PCI0) {
External(TOM1, IntObj) /* Generated by root_complex.c */
Method(_BBN, 0, NotSerialized) {
Return(Zero) /* Bus number = 0 */
Return(0) /* Bus number = 0 */
}
Method(_STA, 0, NotSerialized) {

2
src/soc/amd/mendocino/acpi/pci0.asl
View File

@ -8,7 +8,7 @@ Device(PCI0) {
External(TOM1, IntObj) /* Generated by root_complex.c */
Method(_BBN, 0, NotSerialized) {
Return(Zero) /* Bus number = 0 */
Return(0) /* Bus number = 0 */
}
Method(_STA, 0, NotSerialized) {

2
src/soc/amd/morgana/acpi/pci0.asl
View File

@ -8,7 +8,7 @@ Device(PCI0) {
External(TOM1, IntObj) /* Generated by root_complex.c */
Method(_BBN, 0, NotSerialized) {
Return(Zero) /* Bus number = 0 */
Return(0) /* Bus number = 0 */
}
Method(_STA, 0, NotSerialized) {

2
src/soc/amd/picasso/acpi/northbridge.asl
View File

@ -10,7 +10,7 @@ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
Method(_BBN, 0, NotSerialized) /* Bus number = 0 */
{
Return(Zero)
Return(0)
}
Method(_STA, 0, NotSerialized)

2
src/soc/amd/stoneyridge/acpi/northbridge.asl
View File

@ -10,7 +10,7 @@ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
Method(_BBN, 0, NotSerialized) /* Bus number = 0 */
{
Return(Zero)
Return(0)
}
Method(_STA, 0, NotSerialized)

18
src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
View File

@ -410,7 +410,7 @@ Method(FDDC, 2, Serialized)
Switch(ToInteger(Arg0))
{
Case(5) {
I0PD = Zero
I0PD = 0
Local0 = I0DS
while(Local0 != 0x0) {
Local0 = I0DS
@ -418,7 +418,7 @@ Method(FDDC, 2, Serialized)
I0TD = 0x03
}
Case(6) {
I1PD = Zero
I1PD = 0
Local0 = I1DS
while(Local0 != 0x0) {
Local0 = I1DS
@ -426,7 +426,7 @@ Method(FDDC, 2, Serialized)
I1TD = 0x03
}
Case(7) {
I2PD = Zero
I2PD = 0
Local0 = I2DS
while(Local0 != 0x0) {
Local0 = I2DS
@ -434,7 +434,7 @@ Method(FDDC, 2, Serialized)
I2TD = 0x03
}
Case(8) {
I3PD = Zero
I3PD = 0
Local0 = I3DS
while(Local0 != 0x0) {
Local0 = I3DS
@ -442,7 +442,7 @@ Method(FDDC, 2, Serialized)
I3TD = 0x03
}
Case(11) {
U0PD = Zero
U0PD = 0
Local0 = U0DS
while(Local0 != 0x0) {
Local0 = U0DS
@ -450,7 +450,7 @@ Method(FDDC, 2, Serialized)
U0TD = 0x03
}
Case(12) {
U1PD = Zero
U1PD = 0
Local0 = U1DS
while(Local0 != 0x0) {
Local0 = U1DS
@ -461,7 +461,7 @@ Method(FDDC, 2, Serialized)
Case(18) { U2D3()} /* EHCI */
Case(23) { U3D3()} /* XHCI */
Case(24) { /* SD */
SDPD = Zero
SDPD = 0
Local0 = SDDS
while(Local0 != 0x0) {
Local0 = SDDS
@ -472,7 +472,7 @@ Method(FDDC, 2, Serialized)
/* Turn off Power */
if (I0TD == 3) {
if (SATD == 3) {
if (SDTD == 3) { PG1A = Zero }
if (SDTD == 3) { PG1A = 0 }
}
}
if (I1TD == 3) {
@ -481,7 +481,7 @@ Method(FDDC, 2, Serialized)
if (U0TD == 3) {
if (U1TD == 3) {
if (U2TD == 3) {
PG2_ = Zero
PG2_ = 0
}
}
}

38
src/soc/amd/stoneyridge/acpi/usb.asl
View File

@ -5,7 +5,7 @@ Device(EHC0) {
Name(_ADR, 0x00120000)
Name(_PRW, Package() { 0xb, 3 })
Device (RHUB) {
Name (_ADR, Zero)
Name (_ADR, 0)
Device (HS01) { Name (_ADR, 1) }
Device (HS02) { Name (_ADR, 2) }
Device (HS03) { Name (_ADR, 3) }
@ -121,14 +121,14 @@ Field(EHMC, DwordAcc, NoLock, Preserve)
Method(U2D3,0, Serialized)
{
if (EH10 != Zero) {
if (EH10 != 0) {
EHBA = EH10
EHME = 1
SSIM = ESIM
}
if (E_PS == 3) {
RQTY = Zero
RQTY = 0
RQ18 = 1
Local0 = U2SR
@ -136,10 +136,10 @@ Method(U2D3,0, Serialized)
Local0 = U2SR
}
U2PD = Zero
U2PD = 0
Local0 = U2DS
while (Local0 != Zero) {
while (Local0 != 0) {
Local0 = U2DS
}
@ -155,10 +155,10 @@ Method(U2D3,0, Serialized)
Method(U2D0,0, Serialized)
{
PWGC (0x40, 1)
U2RP = Zero
U2RP = 0
U2TD = 0x00
U2TD = Zero
U2TD = 0
U2PD = 1
Local0 = U2DS
@ -175,7 +175,7 @@ Method(U2D0,0, Serialized)
EH2C = EHID
if (EH10 != Zero) {
if (EH10 != 0) {
EHBA = EH10
EHME = 1
ESIM = SSIM
@ -196,7 +196,7 @@ Method(LXFW,3, Serialized) //Load Xhci FirmWare
while (!Local0) {
Local0 = FPLC
}
FPLS = Zero
FPLS = 0
}
Method(U3D3,0, Serialized)
@ -211,7 +211,7 @@ Method(U3D3,0, Serialized)
}
UD3P = 1 /* U3P_D3Cold_PWRDN */
U3PD = Zero /* PwrOnDev */
U3PD = 0 /* PwrOnDev */
Local0 = U3DS
while (Local0) { /* RstBState, RefClkOkState, PwrRstBState */
Local0 = U3DS
@ -225,24 +225,24 @@ Method(U3D3,0, Serialized)
PGA3 &= 0x9f /* SwUsb2S5RstB */
U2RP = 1 /* USB2_RefClk_Pwdn */
}
U3PG = Zero /* XhcPwrGood */
U3PG = 0 /* XhcPwrGood */
U3PS = 1 /* Usb3PowerSel */
}
}
Method(U3D0,0, Serialized)
{
U3PS = Zero /* Usb3PowerSel */
U3PS = 0 /* Usb3PowerSel */
U3PG = 1 /* XhcPwrGood */
U2RP = Zero
U3RP = Zero
U2RP = 0
U3RP = 0
Local0 = PGA3 & 0xdf
Local0 |= 0x40
PGA3 = Local0 /* SwUsb2S5RstB */
U3TD = Zero /* TargetedDeviceState */
U3TD = 0 /* TargetedDeviceState */
U3PD = 1 /* PwrOnDev */
Local0 = U3DS /* wait for RstBState, RefClkOkState, PwrRstBState */
@ -255,7 +255,7 @@ Method(U3D0,0, Serialized)
Local0 = U3PY
}
U3PR = Zero /* U3P_RESTORE_RESET */
U3PR = 0 /* U3P_RESTORE_RESET */
Local0 = AUSS /* AutoSizeStart */
if (Local0 != 1) {
@ -272,7 +272,7 @@ Method(U3D0,0, Serialized)
X0_R ()
U3PR = 1 /* U3P_RESTORE_RESET */
UD3P = Zero /* U3P_D3Cold_PWRDN */
UD3P = 0 /* U3P_D3Cold_PWRDN */
U3TD = 1 /* TargetedDeviceState */
}
@ -314,7 +314,7 @@ CreateDWordField(SVBF, 0x7B0, SSIM) /* EHCI SIM BIT */
Method(X0_S,0)
{
XHID = XH2C
IDEX = Zero
IDEX = 0
S000 = DATA
IDEX = 0x00000004
S004 = DATA
@ -375,7 +375,7 @@ Method(X0_S,0)
Method(X0_R,0)
{
XH2C = XHID
IDEX = Zero
IDEX = 0
DATA = S000
IDEX = 0x000000004
DATA = S004

2
src/soc/intel/alderlake/acpi/tcss_xhci.asl
View File

@ -109,7 +109,7 @@ Method (_DSW, 3)
*/
Device (RHUB)
{
Name (_ADR, Zero)
Name (_ADR, 0)
/* High Speed Ports */
Device (HS01)

4
src/soc/intel/alderlake/acpi/xhci.asl
View File

@ -27,7 +27,7 @@ Device (XHCI)
/* Root Hub for Alder Lake-P PCH */
Device (RHUB)
{
Name (_ADR, Zero)
Name (_ADR, 0)
/* USB2 */
Device (HS01) { Name (_ADR, 1) }
@ -60,7 +60,7 @@ Device (XHCI)
/* Root Hub for Alder Lake-P PCH */
Device (RHUB)
{
Name (_ADR, Zero)
Name (_ADR, 0)
/* USB2 */
Device (HS01) { Name (_ADR, 1) }

2
src/soc/intel/apollolake/acpi/xhci.asl
View File

@ -19,7 +19,7 @@ Device (XHCI) {
Device (RHUB)
{
/* Root Hub */
Name (_ADR, Zero)
Name (_ADR, 0)
#if CONFIG(SOC_INTEL_GEMINILAKE)
#include "xhci_glk_ports.asl"

2
src/soc/intel/baytrail/acpi/dptf/charger.asl
View File

@ -30,7 +30,7 @@ Device (TCHG)
Local0--
/* Check if charging is disabled (AC removed) */
If (\PWRS == Zero) {
If (\PWRS == 0) {
/* Return last power state */
Return (Local0)
} Else {

16
src/soc/intel/baytrail/acpi/irqlinks.asl
View File

@ -28,7 +28,7 @@ Device (LNKA)
CreateWordField(RTLA, 1, IRQ0)
/* Clear the WordField */
IRQ0 = Zero
IRQ0 = 0
/* Set the bit from PRTA */
IRQ0 = 1 << (PRTA & 0x0f)
@ -87,7 +87,7 @@ Device (LNKB)
CreateWordField(RTLB, 1, IRQ0)
/* Clear the WordField */
IRQ0 = Zero
IRQ0 = 0
/* Set the bit from PRTB */
IRQ0 = 1 << (PRTB & 0x0f)
@ -146,7 +146,7 @@ Device (LNKC)
CreateWordField(RTLC, 1, IRQ0)
/* Clear the WordField */
IRQ0 = Zero
IRQ0 = 0
/* Set the bit from PRTC */
IRQ0 = 1 << (PRTC & 0x0f)
@ -205,7 +205,7 @@ Device (LNKD)
CreateWordField(RTLD, 1, IRQ0)
/* Clear the WordField */
IRQ0 = Zero
IRQ0 = 0
/* Set the bit from PRTD */
IRQ0 = 1 << (PRTD & 0x0f)
@ -264,7 +264,7 @@ Device (LNKE)
CreateWordField(RTLE, 1, IRQ0)
/* Clear the WordField */
IRQ0 = Zero
IRQ0 = 0
/* Set the bit from PRTE */
IRQ0 = 1 << (PRTE & 0x0f)
@ -323,7 +323,7 @@ Device (LNKF)
CreateWordField(RTLF, 1, IRQ0)
/* Clear the WordField */
IRQ0 = Zero
IRQ0 = 0
/* Set the bit from PRTF */
IRQ0 = 1 << (PRTF & 0x0f)
@ -382,7 +382,7 @@ Device (LNKG)
CreateWordField(RTLG, 1, IRQ0)
/* Clear the WordField */
IRQ0 = Zero
IRQ0 = 0
/* Set the bit from PRTG */
IRQ0 = 1 << (PRTG & 0x0f)
@ -441,7 +441,7 @@ Device (LNKH)
CreateWordField(RTLH, 1, IRQ0)
/* Clear the WordField */
IRQ0 = Zero
IRQ0 = 0
/* Set the bit from PRTH */
IRQ0 = 1 << (PRTH & 0x0f)

8
src/soc/intel/baytrail/acpi/southcluster.asl
View File

@ -155,7 +155,7 @@ Method (_CRS, 0, Serialized)
CreateDWordField (MCRS, ^LMEM._MIN, LMIN)
CreateDWordField (MCRS, ^LMEM._MAX, LMAX)
CreateDWordField (MCRS, ^LMEM._LEN, LLEN)
If (LPFW != Zero && LPEN == 1)
If (LPFW != 0 && LPEN == 1)
{
LMIN = LPFW
LLEN = 0x00100000
@ -163,9 +163,9 @@ Method (_CRS, 0, Serialized)
}
Else
{
LMIN = Zero
LMAX = Zero
LLEN = Zero
LMIN = 0
LMAX = 0
LLEN = 0
}
/* Update PCI resource area */

2
src/soc/intel/baytrail/acpi/xhci.asl
View File

@ -17,7 +17,7 @@ Device (XHCI)
})
// REV: Revision 0x02 for ACPI 5.0
CreateField (DerefOf (PCKG[0]), Zero, 0x07, REV)
CreateField (DerefOf (PCKG[0]), 0, 0x07, REV)
REV = 0x02
// VISI: Port visibility to user per port

2
src/soc/intel/braswell/acpi/dptf/charger.asl
View File

@ -30,7 +30,7 @@ Device (TCHG)
Local0--
/* Check if charging is disabled (AC removed) */
If (\_SB.PCI0.LPCB.EC0.ACEX == Zero) {
If (\_SB.PCI0.LPCB.EC0.ACEX == 0) {
/* Return last power state */
Return (Local0)
} Else {

16
src/soc/intel/braswell/acpi/irqlinks.asl
View File

@ -28,7 +28,7 @@ Device (LNKA)
CreateWordField(RTLA, 1, IRQ0)
/* Clear the WordField */
IRQ0 = Zero
IRQ0 = 0
/* Set the bit from PRTA */
IRQ0 = 1 << (PRTA & 0x0f)
@ -87,7 +87,7 @@ Device (LNKB)
CreateWordField(RTLB, 1, IRQ0)
/* Clear the WordField */
IRQ0 = Zero
IRQ0 = 0
/* Set the bit from PRTB */
IRQ0 = 1 << (PRTB & 0x0f)
@ -146,7 +146,7 @@ Device (LNKC)
CreateWordField(RTLC, 1, IRQ0)
/* Clear the WordField */
IRQ0 = Zero
IRQ0 = 0
/* Set the bit from PRTC */
IRQ0 = 1 << (PRTC & 0x0f)
@ -205,7 +205,7 @@ Device (LNKD)
CreateWordField(RTLD, 1, IRQ0)
/* Clear the WordField */
IRQ0 = Zero
IRQ0 = 0
/* Set the bit from PRTD */
IRQ0 = 1 << (PRTD & 0x0f)
@ -264,7 +264,7 @@ Device (LNKE)
CreateWordField(RTLE, 1, IRQ0)
/* Clear the WordField */
IRQ0 = Zero
IRQ0 = 0
/* Set the bit from PRTE */
IRQ0 = 1 << (PRTE & 0x0f)
@ -323,7 +323,7 @@ Device (LNKF)
CreateWordField(RTLF, 1, IRQ0)
/* Clear the WordField */
IRQ0 = Zero
IRQ0 = 0
/* Set the bit from PRTF */
IRQ0 = 1 << (PRTF & 0x0f)
@ -382,7 +382,7 @@ Device (LNKG)
CreateWordField(RTLG, 1, IRQ0)
/* Clear the WordField */
IRQ0 = Zero
IRQ0 = 0
/* Set the bit from PRTG */
IRQ0 = 1 << (PRTG & 0x0f)
@ -441,7 +441,7 @@ Device (LNKH)
CreateWordField(RTLH, 1, IRQ0)
/* Clear the WordField */
IRQ0 = Zero
IRQ0 = 0
/* Set the bit from PRTH */
IRQ0 = 1 << (PRTH & 0x0f)

2
src/soc/intel/braswell/acpi/scc.asl
View File

@ -96,7 +96,7 @@ Device (PEMC)
Name (_ADR, 0x08)
Method (_RMV, 0, NotSerialized)
{
Return (Zero)
Return (0)
}
}
}

8
src/soc/intel/braswell/acpi/southcluster.asl
View File

@ -154,7 +154,7 @@ Method (_CRS, 0, Serialized)
CreateDWordField (MCRS, LMEM._MIN, LMIN)
CreateDWordField (MCRS, LMEM._MAX, LMAX)
CreateDWordField (MCRS, LMEM._LEN, LLEN)
If (LPFW != Zero && LPEN == 1)
If (LPFW != 0 && LPEN == 1)
{
LMIN = LPFW
LMAX = LMIN + 0x001FFFFF
@ -162,9 +162,9 @@ Method (_CRS, 0, Serialized)
}
Else
{
LMIN = Zero
LMAX = Zero
LLEN = Zero
LMIN = 0
LMAX = 0
LLEN = 0
}
/* Update PCI resource area */

4
src/soc/intel/cannonlake/acpi/xhci.asl
View File

@ -48,7 +48,7 @@ Method (UWES, 3, Serialized)
While (1) {
FindSetRightBit (Local0, Local1)
If (Local1 == Zero) {
If (Local1 == 0) {
Break
}
UPWE (Local1, Arg1, Arg2)
@ -102,7 +102,7 @@ Device (XHCI)
/* Root Hub for Cannonlake-LP PCH */
Device (RHUB)
{
Name (_ADR, Zero)
Name (_ADR, 0)
/* USB2 */
Device (HS01) { Name (_ADR, 1) }

2
src/soc/intel/common/acpi/wifi.asl
View File

@ -2,7 +2,7 @@
Device (WIFI)
{
Name (_ADR, Zero)
Name (_ADR, 0)
OperationRegion(WIXX, PCI_Config, 0x00, 0x10)
Name (WRDX, Package()
{

4
src/soc/intel/common/block/acpi/acpi/northbridge.asl
View File

@ -5,8 +5,8 @@
Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, Zero) // _SEG: PCI Segment
Name (_UID, Zero) // _UID: Unique ID
Name (_SEG, 0) // _SEG: PCI Segment
Name (_UID, 0) // _UID: Unique ID
Device (MCHC)
{

4
src/soc/intel/elkhartlake/acpi/pch_hda.asl
View File

@ -31,12 +31,12 @@ Device (HDAS)
* Function 0: Function Support Query
* Returns a bitmask of functions supported.
*/
If (Arg2 == Zero) {
If (Arg2 == 0) {
/*
* NHLT Query only supported for revision 1 and
* if NHLT address and length are set in NVS.
*/
If ((Arg1 == 1) && ((NHLA != Zero) && (NHLL != Zero))) {
If ((Arg1 == 1) && ((NHLA != 0) && (NHLL != 0))) {
Return (Buffer (1) { 0x03 })
} Else {
Return (Buffer (1) { 0x01 })

2
src/soc/intel/elkhartlake/acpi/xhci.asl
View File

@ -27,7 +27,7 @@ Device (XHCI)
/* Root Hub for Elkhartlake PCH */
Device (RHUB)
{
Name (_ADR, Zero)
Name (_ADR, 0)
/* USB2 */
Device (HS01) { Name (_ADR, 1) }

4
src/soc/intel/icelake/acpi/pch_hda.asl
View File

@ -31,12 +31,12 @@ Device (HDAS)
* Function 0: Function Support Query
* Returns a bitmask of functions supported.
*/
If (Arg2 == Zero) {
If (Arg2 == 0) {
/*
* NHLT Query only supported for revision 1 and
* if NHLT address and length are set in NVS.
*/
If (Arg1 == 1 && NHLA != Zero && NHLL != Zero) {
If (Arg1 == 1 && NHLA != 0 && NHLL != 0) {
Return (Buffer (1) { 0x03 })
} Else {
Return (Buffer (1) { 0x01 })

2
src/soc/intel/icelake/acpi/xhci.asl
View File

@ -27,7 +27,7 @@ Device (XHCI)
/* Root Hub for Icelake-LP PCH */
Device (RHUB)
{
Name (_ADR, Zero)
Name (_ADR, 0)
/* USB2 */
Device (HS01) { Name (_ADR, 1) }

4
src/soc/intel/jasperlake/acpi/pch_hda.asl
View File

@ -31,12 +31,12 @@ Device (HDAS)
* Function 0: Function Support Query
* Returns a bitmask of functions supported.
*/
If (Arg2 == Zero) {
If (Arg2 == 0) {
/*
* NHLT Query only supported for revision 1 and
* if NHLT address and length are set in NVS.
*/
If ((Arg1 == 1) && ((NHLA != Zero) && (NHLL != Zero))) {
If ((Arg1 == 1) && ((NHLA != 0) && (NHLL != 0))) {
Return (Buffer (1) { 0x03 })
} Else {
Return (Buffer (1) { 0x01 })

2
src/soc/intel/jasperlake/acpi/xhci.asl
View File

@ -27,7 +27,7 @@ Device (XHCI)
/* Root Hub for Jasperlake PCH */
Device (RHUB)
{
Name (_ADR, Zero)
Name (_ADR, 0)
/* USB2 */
Device (HS01) { Name (_ADR, 1) }

2
src/soc/intel/meteorlake/acpi/tcss_xhci.asl
View File

@ -103,7 +103,7 @@ Method (_DSW, 3)
*/
Device (RHUB)
{
Name (_ADR, Zero)
Name (_ADR, 0)
/* High Speed Ports */
Device (HS01)

2
src/soc/intel/meteorlake/acpi/xhci.asl
View File

@ -27,7 +27,7 @@ Device (XHCI)
/* Root Hub for Meteorlake */
Device (RHUB)
{
Name (_ADR, Zero)
Name (_ADR, 0)
/* USB2 */
Device (HS01) { Name (_ADR, 1) }

4
src/soc/intel/skylake/acpi/systemagent.asl
View File

@ -5,8 +5,8 @@
Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, Zero) // _SEG: PCI Segment
Name (_UID, Zero) // _UID: Unique ID
Name (_SEG, 0) // _SEG: PCI Segment
Name (_UID, 0) // _UID: Unique ID
Device (MCHC)
{

6
src/soc/intel/skylake/acpi/xhci.asl
View File

@ -46,7 +46,7 @@ Method (UWES, 3, Serialized)
While (1) {
FindSetRightBit (Local0, Local1)
If (Local1 == Zero) {
If (Local1 == 0) {
Break
}
UPWE (Local1, Arg1, Arg2)
@ -209,7 +209,7 @@ Device (XHCI)
/* Root Hub for Skylake-LP PCH */
Device (RHUB)
{
Name (_ADR, Zero)
Name (_ADR, 0)
// GPLD: Generate Port Location Data (PLD)
Method (GPLD, 1, Serialized)
@ -221,7 +221,7 @@ Device (XHCI)
})
// REV: Revision 0x02 for ACPI 5.0
CreateField (DerefOf (PCKG[0]), Zero, 0x07, REV)
CreateField (DerefOf (PCKG[0]), 0, 0x07, REV)
REV = 0x02
// VISI: Port visibility to user per port

2
src/soc/intel/tigerlake/acpi/tcss_xhci.asl
View File

@ -109,7 +109,7 @@ Method (_DSW, 3)
*/
Device (RHUB)
{
Name (_ADR, Zero)
Name (_ADR, 0)
/* High Speed Ports */
Device (HS01)

4
src/soc/intel/tigerlake/acpi/xhci.asl
View File

@ -28,7 +28,7 @@ Device (XHCI)
/* Root Hub for Tigerlake-H PCH */
Device (RHUB)
{
Name (_ADR, Zero)
Name (_ADR, 0)
/* USB2 */
Device (HS01) { Name (_ADR, 1) }
@ -62,7 +62,7 @@ Device (XHCI)
/* Root Hub for Tigerlake-LP PCH */
Device (RHUB)
{
Name (_ADR, Zero)
Name (_ADR, 0)
/* USB2 */
Device (HS01) { Name (_ADR, 1) }

10
src/vendorcode/google/chromeos/acpi/amac.asl
View File

@ -29,22 +29,22 @@ Scope (\_SB)
/* Get "dock_passthrough" value from RW_VPD */
Local0 = \VPD.VPDF ("RW", "dock_passthrough")
Local1 = Zero
Local1 = 0
Switch (ToString (Local0))
{
Case ("ethernet_mac0") {
Local1 = \VPD.VPDF ("RO", "ethernet_mac0")
}
Case ("builtin") {
Return (Zero)
Return (0)
}
/* "dock_mac" or policy not found. */
Default {
Local1 = \VPD.VPDF ("RO", "dock_mac")
}
}
If (Local1 == Zero) {
Return (Zero)
If (Local1 == 0) {
Return (0)
}
Printf ("MAC address returned from VPD: %o", Local1)
@ -52,7 +52,7 @@ Scope (\_SB)
For (Local3 = 2, Local3 < 17, Local3 += 3) {
If (ToString (DerefOf (Local1[Local3])) != ":") {
Printf ("Invalid MAC address byte %o", Local3)
Return (Zero)
Return (0)
}
}