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soc/intel/alderlake: Unselect USB4 and TCSS options for ADL-S 

Alder Lake-S CPUs do not have TCSS and USB4 devices. Unselect them.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ifc643d440107754dfe1a0844964f70de670cb1f1
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Michał Żygowski 2022-04-08 17:02:35 +02:00 committed by Felix Held
parent bda2a15113
commit 9df95d99dc
2 changed files with 10 additions and 5 deletions
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13
src/soc/intel/alderlake/Kconfig
View File

@ -105,11 +105,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_TCSS
select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC
select SOC_INTEL_COMMON_BLOCK_USB4
select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_BASECODE
@ -126,6 +122,15 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_TSC
select UDK_202005_BINDING
config SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT
bool
default y if !SOC_INTEL_ALDERLAKE_PCH_S
default n if SOC_INTEL_ALDERLAKE_PCH_S
select SOC_INTEL_COMMON_BLOCK_TCSS
select SOC_INTEL_COMMON_BLOCK_USB4
select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
config ALDERLAKE_CONFIGURE_DESCRIPTOR
bool
help

2
src/soc/intel/alderlake/Makefile.inc
View File

@ -40,7 +40,7 @@ ramstage-y += p2sb.c
ramstage-y += pcie_rp.c
ramstage-y += pmc.c
ramstage-y += reset.c
ramstage-y += retimer.c
ramstage-$(CONFIG_SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT) += retimer.c
ramstage-y += soundwire.c
ramstage-y += systemagent.c
ramstage-y += tcss.c