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mainboard/google/zoombini/variant/meowth: add PCH_WP_OD 

Configure GPP_H12 as an input for PCH_WP_OD.

BUG=b:72202352
BRANCH=none
TEST=none

Change-Id: Ie5b60644a24d745add4d0d38c1421974b8a0017b
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Nick Vaccaro 2018-01-21 22:11:52 -08:00 committed by Martin Roth
parent 25794d2a65
commit 9e17e11d8d
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h
View File

@ -29,7 +29,7 @@
#define GPIO_EC_IN_RW GPP_A8 #define GPIO_EC_IN_RW GPP_A8
/* BIOS Flash Write Protect */ /* BIOS Flash Write Protect */
#define GPIO_PCH_WP GPP_A1 #define GPIO_PCH_WP GPP_H12
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
#define GPE_EC_WAKE GPE0_LAN_WAK #define GPE_EC_WAKE GPE0_LAN_WAK

2
src/mainboard/google/zoombini/variants/meowth/gpio.c
View File

@ -226,7 +226,7 @@ static const struct pad_config gpio_table[] = {
NF1), /* PCH_RCAM_SAR0_I2C5_SDA */ NF1), /* PCH_RCAM_SAR0_I2C5_SDA */
/* I2C5_SCL */ PAD_CFG_NF(GPP_H11, NONE, DEEP, /* I2C5_SCL */ PAD_CFG_NF(GPP_H11, NONE, DEEP,
NF1), /* PCH_RCAM_SAR0_I2C5_SCL */ NF1), /* PCH_RCAM_SAR0_I2C5_SCL */
/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), /* M2_SKT2_CFG0 */ PAD_CFG_GPI(GPP_H12, NONE, DEEP), /* PCH_WP_OD */
/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), /* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE),
/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE),
/* M2_SKT2_CFG3 */ PAD_NC(GPP_H15, NONE), /* M2_SKT2_CFG3 */ PAD_NC(GPP_H15, NONE),