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Move register block definitions out of board code into 

chipset code (where it belongs)

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2010-11-18 10:48:15 +00:00 committed by Patrick Georgi
parent d4917692ec
commit 9e180387bd
3 changed files with 20 additions and 22 deletions
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7
src/mainboard/intel/eagleheights/romstage.c
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@ -41,16 +41,11 @@
#include "superio/intel/i3100/i3100_early_serial.c" #include "superio/intel/i3100/i3100_early_serial.c"
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
#include "northbridge/intel/i3100/i3100.h" #include "northbridge/intel/i3100/i3100.h"
#include "southbridge/intel/i3100/i3100.h"
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
/* SATA */
#define SATA_MAP 0x90
#define SATA_MODE_IDE 0x00
#define SATA_MODE_AHCI 0x01
#define RCBA_RPC 0x0224 /* 32 bit */ #define RCBA_RPC 0x0224 /* 32 bit */
#define RCBA_TCTL 0x3000 /* 8 bit */ #define RCBA_TCTL 0x3000 /* 8 bit */

19
src/southbridge/intel/i3100/i3100.h
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@ -21,6 +21,25 @@
#define SOUTHBRIDGE_INTEL_I3100_I3100_H #define SOUTHBRIDGE_INTEL_I3100_I3100_H
#include "chip.h" #include "chip.h"
#define SATA_CMD 0x04
#define SATA_PI 0x09
#define SATA_PTIM 0x40
#define SATA_STIM 0x42
#define SATA_D1TIM 0x44
#define SATA_SYNCC 0x48
#define SATA_SYNCTIM 0x4A
#define SATA_IIOC 0x54
#define SATA_MAP 0x90
#define SATA_PCS 0x91
#define SATA_ACR0 0xA8
#define SATA_ACR1 0xAC
#define SATA_ATC 0xC0
#define SATA_ATS 0xC4
#define SATA_SP 0xD0
#define SATA_MODE_IDE 0x00
#define SATA_MODE_AHCI 0x01
void i3100_enable(device_t dev); void i3100_enable(device_t dev);
#endif #endif

16
src/southbridge/intel/i3100/i3100_sata.c
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@ -27,22 +27,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include "i3100.h" #include "i3100.h"
#define SATA_CMD 0x04
#define SATA_PI 0x09
#define SATA_PTIM 0x40
#define SATA_STIM 0x42
#define SATA_D1TIM 0x44
#define SATA_SYNCC 0x48
#define SATA_SYNCTIM 0x4A
#define SATA_IIOC 0x54
#define SATA_MAP 0x90
#define SATA_PCS 0x91
#define SATA_ACR0 0xA8
#define SATA_ACR1 0xAC
#define SATA_ATC 0xC0
#define SATA_ATS 0xC4
#define SATA_SP 0xD0
typedef struct southbridge_intel_i3100_config config_t; typedef struct southbridge_intel_i3100_config config_t;
static void sata_init(struct device *dev) static void sata_init(struct device *dev)