Move register block definitions out of board code into
chipset code (where it belongs) Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -41,16 +41,11 @@
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#include "superio/intel/i3100/i3100_early_serial.c"
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#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
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#include "northbridge/intel/i3100/i3100.h"
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#include "southbridge/intel/i3100/i3100.h"
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#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
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#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
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/* SATA */
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#define SATA_MAP 0x90
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#define SATA_MODE_IDE 0x00
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#define SATA_MODE_AHCI 0x01
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#define RCBA_RPC 0x0224 /* 32 bit */
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#define RCBA_TCTL 0x3000 /* 8 bit */
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@ -21,6 +21,25 @@
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#define SOUTHBRIDGE_INTEL_I3100_I3100_H
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#include "chip.h"
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#define SATA_CMD 0x04
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#define SATA_PI 0x09
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#define SATA_PTIM 0x40
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#define SATA_STIM 0x42
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#define SATA_D1TIM 0x44
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#define SATA_SYNCC 0x48
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#define SATA_SYNCTIM 0x4A
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#define SATA_IIOC 0x54
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#define SATA_MAP 0x90
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#define SATA_PCS 0x91
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#define SATA_ACR0 0xA8
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#define SATA_ACR1 0xAC
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#define SATA_ATC 0xC0
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#define SATA_ATS 0xC4
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#define SATA_SP 0xD0
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#define SATA_MODE_IDE 0x00
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#define SATA_MODE_AHCI 0x01
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void i3100_enable(device_t dev);
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#endif
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@ -27,22 +27,6 @@
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#include <device/pci_ops.h>
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#include "i3100.h"
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#define SATA_CMD 0x04
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#define SATA_PI 0x09
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#define SATA_PTIM 0x40
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#define SATA_STIM 0x42
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#define SATA_D1TIM 0x44
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#define SATA_SYNCC 0x48
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#define SATA_SYNCTIM 0x4A
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#define SATA_IIOC 0x54
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#define SATA_MAP 0x90
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#define SATA_PCS 0x91
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#define SATA_ACR0 0xA8
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#define SATA_ACR1 0xAC
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#define SATA_ATC 0xC0
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#define SATA_ATS 0xC4
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#define SATA_SP 0xD0
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typedef struct southbridge_intel_i3100_config config_t;
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static void sata_init(struct device *dev)
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