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mediatek/mt8183: Support gpio eh and rsel setting for I2C

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The setting of these registers are only for i2c pin.

BUG=b:80501386
BRANCH=none
TEST=Boot correctly on Kukui

Change-Id: I518ca07645fe55aa55e94e4f98178baa0b74a882
Signed-off-by: jg_poxu <jg_poxu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/30974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
jg_poxu 2019-01-31 15:46:03 +08:00 committed by Julius Werner
parent 187e4c4474
commit 9e21b2dbd7
2 changed files with 62 additions and 0 deletions
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61
src/soc/mediatek/mt8183/gpio.c
View file

@ -19,6 +19,7 @@
enum {
EN_OFFSET = 0x60,
SEL_OFFSET = 0x80,
EH_RSEL_OFFSET = 0xF0,
};
static void gpio_set_pull_pupd(gpio_t gpio, enum pull_enable enable,
@ -67,3 +68,63 @@ void gpio_set_pull(gpio_t gpio, enum pull_enable enable,
else
gpio_set_pull_en_sel(gpio, enable, select);
}
enum {
EH_VAL = 0x0,
RSEL_VAL = 0x3,
EH_MASK = 0x7,
RSEL_MASK = 0x3,
SCL0_EH = 19,
SCL0_RSEL = 15,
SDA0_EH = 9,
SDA0_RSEL = 5,
SCL1_EH = 22,
SCL1_RSEL = 17,
SDA1_EH = 12,
SDA1_RSEL = 7,
SCL2_EH = 24,
SCL2_RSEL = 20,
SDA2_EH = 14,
SDA2_RSEL = 10,
SCL3_EH = 12,
SCL3_RSEL = 10,
SDA3_EH = 7,
SDA3_RSEL = 5,
SCL4_EH = 27,
SCL4_RSEL = 22,
SDA4_EH = 17,
SDA4_RSEL = 12,
SCL5_EH = 20,
SCL5_RSEL = 18,
SDA5_EH = 15,
SDA5_RSEL = 13,
};
#define I2C_EH_RSL_MASK(name) \
(EH_MASK << name##_EH | RSEL_MASK << name##_RSEL)
#define I2C_EH_RSL_VAL(name) \
(EH_VAL << name##_EH | RSEL_VAL << name##_RSEL)
void gpio_set_i2c_eh_rsel(void)
{
clrsetbits_le32((void *)IOCFG_RB_BASE + EH_RSEL_OFFSET,
I2C_EH_RSL_MASK(SCL0) | I2C_EH_RSL_MASK(SDA0) |
I2C_EH_RSL_MASK(SCL1) | I2C_EH_RSL_MASK(SDA1),
I2C_EH_RSL_VAL(SCL0) | I2C_EH_RSL_VAL(SDA0) |
I2C_EH_RSL_VAL(SCL1) | I2C_EH_RSL_VAL(SDA1));
clrsetbits_le32((void *)IOCFG_RM_BASE + EH_RSEL_OFFSET,
I2C_EH_RSL_MASK(SCL2) | I2C_EH_RSL_MASK(SDA2) |
I2C_EH_RSL_MASK(SCL4) | I2C_EH_RSL_MASK(SDA4),
I2C_EH_RSL_VAL(SCL2) | I2C_EH_RSL_VAL(SDA2) |
I2C_EH_RSL_VAL(SCL4) | I2C_EH_RSL_VAL(SDA4));
clrsetbits_le32((void *)IOCFG_BL_BASE + EH_RSEL_OFFSET,
I2C_EH_RSL_MASK(SCL3) | I2C_EH_RSL_MASK(SDA3),
I2C_EH_RSL_VAL(SCL3) | I2C_EH_RSL_VAL(SDA3));
clrsetbits_le32((void *)IOCFG_LB_BASE + EH_RSEL_OFFSET,
I2C_EH_RSL_MASK(SCL5) | I2C_EH_RSL_MASK(SDA5),
I2C_EH_RSL_VAL(SCL5) | I2C_EH_RSL_VAL(SDA5));
}

1
src/soc/mediatek/mt8183/include/soc/gpio.h
View file

@ -616,5 +616,6 @@ struct gpio_regs {
check_member(gpio_regs, mode[22].val, 0x460);
static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE);
void gpio_set_i2c_eh_rsel(void);
#endif