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superio/winbond/w83627ehg: Convert romstage to generic component 

Convert the serial init to the generic romstage component and
corresponding boards using this sio.

Change-Id: Ib9f981f43e047013f9cbe20a22246ee2ed3ecf50
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5589
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Edward O'Callaghan 2014-04-27 23:28:31 +10:00 committed by Kyösti Mälkki
parent 959adc3fcf
commit 9e308b9955
9 changed files with 16 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/asus/a8v-e_deluxe/romstage.c
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@ -38,6 +38,7 @@ unsigned int get_sbdn(unsigned bus);
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/early_ht.c" #include "northbridge/amd/amdk8/early_ht.c"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h> #include <superio/winbond/w83627ehg/w83627ehg.h>
#include "southbridge/via/vt8237r/early_smbus.c" #include "southbridge/via/vt8237r/early_smbus.c"
#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
@ -153,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = &sysinfo_car;
sio_init(); sio_init();
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
enable_rom_decode(); enable_rom_decode();
@ -166,11 +167,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain(); enumerate_ht_chain();
} }
sio_init();
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_rom_decode();
print_info("now booting... real_main\n"); print_info("now booting... real_main\n");
if (bist == 0) if (bist == 0)

10
src/mainboard/asus/a8v-e_se/romstage.c
View File

@ -38,6 +38,7 @@ unsigned int get_sbdn(unsigned bus);
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/early_ht.c" #include "northbridge/amd/amdk8/early_ht.c"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h> #include <superio/winbond/w83627ehg/w83627ehg.h>
#include "southbridge/via/vt8237r/early_smbus.c" #include "southbridge/via/vt8237r/early_smbus.c"
#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
@ -153,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = &sysinfo_car;
sio_init(); sio_init();
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
enable_rom_decode(); enable_rom_decode();
@ -166,13 +167,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain(); enumerate_ht_chain();
} }
// FIXME why is this executed again? --->
sio_init();
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_rom_decode();
// <--- FIXME why is this executed again?
print_info("now booting... real_main\n"); print_info("now booting... real_main\n");
if (bist == 0) if (bist == 0)

2
src/mainboard/ibase/mb899/romstage.c
View File

@ -27,11 +27,11 @@
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <lib.h> #include <lib.h>
#include <cbmem.h> #include <cbmem.h>
#include <superio/winbond/common/winbond.h>
#include "superio/winbond/w83627ehg/w83627ehg.h" #include "superio/winbond/w83627ehg/w83627ehg.h"
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>
#include <superio/winbond/w83627ehg/w83627ehg.h>
#include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/i945.h"
#include "northbridge/intel/i945/raminit.h" #include "northbridge/intel/i945/raminit.h"
#include "southbridge/intel/i82801gx/i82801gx.h" #include "southbridge/intel/i82801gx/i82801gx.h"

3
src/mainboard/iei/pm-lx-800-r11/romstage.c
View File

@ -32,6 +32,7 @@
#include <southbridge/amd/cs5536/cs5536.h> #include <southbridge/amd/cs5536/cs5536.h>
#include <southbridge/amd/cs5536/early_smbus.c> #include <southbridge/amd/cs5536/early_smbus.c>
#include <southbridge/amd/cs5536/early_setup.c> #include <southbridge/amd/cs5536/early_setup.c>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h> #include <superio/winbond/w83627ehg/w83627ehg.h>
#include <northbridge/amd/lx/raminit.h> #include <northbridge/amd/lx/raminit.h>
@ -63,7 +64,7 @@ void main(unsigned long bist)
cs5536_early_setup(); cs5536_early_setup();
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
report_bist_failure(bist); report_bist_failure(bist);

3
src/mainboard/msi/ms7260/romstage.c
View File

@ -37,6 +37,7 @@
#include <spd.h> #include <spd.h>
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/reset_test.c"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h> #include <superio/winbond/w83627ehg/w83627ehg.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/debug.c"
@ -122,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
pnp_enter_ext_func_mode(SERIAL_DEV); pnp_enter_ext_func_mode(SERIAL_DEV);
/* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */ /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */
pnp_write_config(SERIAL_DEV, 0x24, 0); pnp_write_config(SERIAL_DEV, 0x24, 0);
w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV); pnp_exit_ext_func_mode(SERIAL_DEV);
setup_mb_resource_map(); setup_mb_resource_map();

3
src/mainboard/msi/ms9282/romstage.c
View File

@ -37,6 +37,7 @@
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/debug.c"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h> #include <superio/winbond/w83627ehg/w83627ehg.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include <spd.h> #include <spd.h>
@ -139,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
} }
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */

3
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -39,6 +39,7 @@
#include "lib/delay.c" #include "lib/delay.c"
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
#include "northbridge/amd/amdfam10/reset_test.c" #include "northbridge/amd/amdfam10/reset_test.c"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h> #include <superio/winbond/w83627ehg/w83627ehg.h>
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/debug.c"
@ -126,7 +127,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf)); pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf));
pnp_exit_ext_func_mode(SERIAL_DEV); pnp_exit_ext_func_mode(SERIAL_DEV);
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */

10
src/superio/winbond/w83627ehg/early_serial.c
View File

@ -35,13 +35,3 @@ void pnp_exit_ext_func_mode(device_t dev)
u16 port = dev >> 8; u16 port = dev >> 8;
outb(0xaa, port); outb(0xaa, port);
} }
void w83627ehg_enable_serial(device_t dev, u16 iobase)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
}

7
src/superio/winbond/w83627ehg/w83627ehg.h
View File

@ -19,8 +19,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#ifndef SUPERIO_WINBOND_W83627EHG_W83627EHG_H #ifndef SUPERIO_WINBOND_W83627EHG_H
#define SUPERIO_WINBOND_W83627EHG_W83627EHG_H #define SUPERIO_WINBOND_W83627EHG_H
#define W83627EHG_FDC 0 /* Floppy */ #define W83627EHG_FDC 0 /* Floppy */
#define W83627EHG_PP 1 /* Parallel port */ #define W83627EHG_PP 1 /* Parallel port */
@ -57,10 +57,9 @@
#if defined(__PRE_RAM__) #if defined(__PRE_RAM__)
void w83627ehg_enable_dev(device_t dev, u16 iobase); void w83627ehg_enable_dev(device_t dev, u16 iobase);
void w83627ehg_disable_dev(device_t dev); void w83627ehg_disable_dev(device_t dev);
void w83627ehg_enable_serial(device_t dev, u16 iobase);
#endif #endif
void pnp_enter_ext_func_mode(device_t dev); void pnp_enter_ext_func_mode(device_t dev);
void pnp_exit_ext_func_mode(device_t dev); void pnp_exit_ext_func_mode(device_t dev);
#endif /* SUPERIO_WINBOND_W83627EHG_W83627EHG_H */ #endif /* SUPERIO_WINBOND_W83627EHG_H */