GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/mediatek: dsi: Fix EoTp flag 

SoC will transmit the EoTp (End of Transmission packet) when
MIPI_DSI_MODE_EOT_PACKET flag is set.

Enabling EoTp will make the line time larger, so the hfp and
hbp should be reduced to keep line time.

BUG=b:168728787
BRANCH=kukui
TEST=Display is normal on Kukui

Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com>
Change-Id: Ifadd0def13cc264e9d39ab9c981fbdc996396bfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Shaoming Chen 2020-12-23 11:45:59 +08:00 committed by Hung-Te Lin
parent b32e4d6763
commit 9e38efc27b
2 changed files with 15 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/soc/mediatek/common/dsi.c
View File

@ -154,8 +154,11 @@ static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes)
break; break;
} }
tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; tmp_reg |= NON_CONTINUOUS_CLK;
if (!(mode_flags & MIPI_DSI_MODE_EOT_PACKET))
tmp_reg |= EOTP_DISABLE;
write32(&dsi0->dsi_txrx_ctrl, tmp_reg); write32(&dsi0->dsi_txrx_ctrl, tmp_reg);
} }
@ -202,6 +205,10 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes,
phy_timing->da_hs_zero + phy_timing->da_hs_exit + 3; phy_timing->da_hs_zero + phy_timing->da_hs_exit + 3;
u32 delta = 12; u32 delta = 12;
if (mode_flags & MIPI_DSI_MODE_EOT_PACKET)
delta += 2;
if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
delta += 6; delta += 6;

6
src/soc/mediatek/common/include/soc/dsi_common.h
View File

@ -118,6 +118,12 @@ enum {
MIX_MODE = BIT(17) MIX_MODE = BIT(17)
}; };
/* DSI_TXRX_CTRL */
enum {
EOTP_DISABLE = BIT(6),
NON_CONTINUOUS_CLK = BIT(16),
};
/* DSI_PSCTRL */ /* DSI_PSCTRL */
enum { enum {
DSI_PS_WC = 0x3fff, DSI_PS_WC = 0x3fff,