diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index fe7b3a229b..548ef3d712 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -428,6 +428,7 @@ config ACPI_ADL_IPU_ES_SUPPORT
 config ALDERLAKE_ENABLE_SOC_WORKAROUND
 	bool
 	default y
+	select SOC_INTEL_UFS_LTR_DISQUALIFY
 	select SOC_INTEL_UFS_OCP_TIMER_DISABLE
 	help
 	  Selects the workarounds applicable for Alder Lake SoC.
diff --git a/src/soc/intel/alderlake/include/soc/ufs.h b/src/soc/intel/alderlake/include/soc/ufs.h
index 3b5e33d0fb..e3a98f2e34 100644
--- a/src/soc/intel/alderlake/include/soc/ufs.h
+++ b/src/soc/intel/alderlake/include/soc/ufs.h
@@ -22,6 +22,7 @@
 #define R_SCS_PCR_5820		0x5820
 #define R_SCS_PCR_5C20		0x5C20
 #define R_SCS_PCR_1078		0x1078
-#define R_PMC_PWRM_LTR_IGN	0x1B0C
 
+#define R_PMC_PWRM_LTR_IGN	0x1b0c
+#define PCH_PWRM_BASE_SIZE	0x1e30
 #endif
diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig
index 2b102bca42..bf5fa569d5 100644
--- a/src/soc/intel/common/block/acpi/Kconfig
+++ b/src/soc/intel/common/block/acpi/Kconfig
@@ -56,4 +56,9 @@ config SOC_INTEL_UFS_OCP_TIMER_DISABLE
 	  work around the Silicon Issue due to which LTR mechanism
 	  doesn't work.
 
+config SOC_INTEL_UFS_LTR_DISQUALIFY
+	bool
+	help
+	  LTR needs to be disqualified for UFS in D3 to ensure PMC
+	  ignores LTR from UFS IP which is infinite.
 endif
diff --git a/src/soc/intel/common/block/acpi/acpi/ufs.asl b/src/soc/intel/common/block/acpi/acpi/ufs.asl
index f7cb9f336e..a2ddaa9c0a 100644
--- a/src/soc/intel/common/block/acpi/acpi/ufs.asl
+++ b/src/soc/intel/common/block/acpi/acpi/ufs.asl
@@ -1,7 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
+#include <soc/iomap.h>
 #include <soc/pcr_ids.h>
 #include <soc/ufs.h>
 
+#define TRUE 1
+#define FALSE 0
+
 Scope (\_SB.PCI0)
 {
 	Device (UFS)
@@ -59,6 +63,18 @@ Scope (\_SB.PCI0)
 			PGEN, 1
 		}
 
+		OperationRegion(PWMR, SystemMemory, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE)
+		Field(PWMR, DWordAcc, NoLock, Preserve)
+		{
+			Offset(R_PMC_PWRM_LTR_IGN),
+			, 18,
+			LTRU,  1,         /* Bit 18 - Ignore LTR from UFS X2 */
+		}
+
+		Method (ULTR, 1, Serialized) {
+			LTRU = Arg0
+		}
+
 		Method (_PS0, 0, Serialized)
 		{
 			/* Disable PG */
@@ -67,6 +83,11 @@ Scope (\_SB.PCI0)
 			/* Set BIT[1:0] = 00b - Power State D0 */
 			PSTA &= 0xFFFFFFFC
 
+#if CONFIG(SOC_INTEL_UFS_LTR_DISQUALIFY)
+			/* Remove Disqualification of LTR from UFS IP */
+			ULTR (FALSE)
+#endif
+
 #if CONFIG(SOC_INTEL_UFS_OCP_TIMER_DISABLE)
 			/* Disable OCP Timer in SCS UFS IOSF Bridge */
 			OCPD ()
@@ -75,6 +96,11 @@ Scope (\_SB.PCI0)
 
 		Method (_PS3, 0, Serialized)
 		{
+#if CONFIG(SOC_INTEL_UFS_LTR_DISQUALIFY)
+			/* Disqualify LTR from UFS IP */
+			ULTR (TRUE)
+#endif
+
 			/* Enable PG */
 			PGEN = 1
 		}