mb/google/brask/variants/moli: set eMMC pin in bootblock
1.Assert eMMC enable pin in bootblock 2.Deassert eMMC reset pin in bootblock BUG=b:220821454 Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I924fcdadaae8ed29b50369a55bad00983cf6ba19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -69,6 +69,8 @@ static const struct pad_config override_gpio_table[] = {
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static const struct pad_config early_gpio_table[] = {
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static const struct pad_config early_gpio_table[] = {
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/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
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/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* B3 : PROC_GP2 ==> EMMC_PERST_L */
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PAD_CFG_GPO(GPP_B3, 0, DEEP),
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 0, DEEP),
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PAD_CFG_GPO(GPP_B4, 0, DEEP),
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/*
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/*
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@ -86,6 +88,8 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_GPO(GPP_D18, 0, PLTRST),
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PAD_CFG_GPO(GPP_D18, 0, PLTRST),
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/* E15 : RSVD_TP ==> PCH_WP_OD */
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/* E15 : RSVD_TP ==> PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
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/* E20 : DDP2_CTRLCLK ==> EN_PP3300_EMMC */
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PAD_CFG_GPO(GPP_E20, 1, DEEP),
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/* F14 : GSXDIN ==> EN_PP3300_SSD */
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/* F14 : GSXDIN ==> EN_PP3300_SSD */
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PAD_CFG_GPO(GPP_F14, 1, DEEP),
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PAD_CFG_GPO(GPP_F14, 1, DEEP),
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/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
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/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
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