soc/amd: Refactor some ACPI S3 calls

Do not pass ACPI S3 state as a parameter, by locally
calling acpi_is_wakeup_s3() compiler has better chance
for optimizing HAVE_ACPI_RESUME=n case.

Test for acpi_s3_allowed() is already included in the
implementation of acpi_is_wakeup_s3() and is removed
as redunandant.

For ramstage, acpi_is_wakeup_s3() evaluates to
romstage_handoff_if_resume().

Change-Id: I6c1e00ec3d5be9a47b9d911c73965bc0c2b17624
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49838
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/kahlee/romstage.c

@@ -1,21 +1,21 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/dimm_spd.h>
+#include <arch/romstage.h>
 #include <baseboard/variants.h>
 #include <soc/gpio.h>
-#include <soc/romstage.h>
 
 int mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len)
 {
 	return variant_mainboard_read_spd(spdAddress, buf, len);
 }
 
-void __weak variant_romstage_entry(int s3_resume)
+void __weak variant_romstage_entry(void)
 {
 	/* By default, don't do anything */
 }
 
-void mainboard_romstage_entry_s3(int s3_resume)
+void mainboard_romstage_entry(void)
 {
 	size_t num_gpios;
 	const struct soc_amd_gpio *gpios;
@@ -23,5 +23,5 @@ void mainboard_romstage_entry_s3(int s3_resume)
 	gpios = variant_romstage_gpio_table(&num_gpios);
 	program_gpios(gpios, num_gpios);
 
-	variant_romstage_entry(s3_resume);
+	variant_romstage_entry();
 }

src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h

@@ -17,7 +17,7 @@ const struct soc_amd_gpio *variant_early_gpio_table(size_t *size);
 const struct soc_amd_gpio *variant_wlan_rst_early_gpio_table(size_t *size);
 const struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size);
 const struct soc_amd_gpio *variant_gpio_table(size_t *size);
-void variant_romstage_entry(int s3_resume);
+void variant_romstage_entry(void);
 void variant_mainboard_suspend_resume(void);
 
 #endif /* __BASEBOARD_VARIANTS_H__ */

src/mainboard/google/kahlee/variants/careena/variant.c

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpi.h>
 #include <ec/google/chromeec/ec.h>
 #include <baseboard/variants.h>
 #include <variant/sku.h>
@@ -17,12 +18,12 @@ const struct soc_amd_gpio *variant_wlan_rst_early_gpio_table(size_t *size)
 	return variant_gpio_wlan_rst_early_reset;
 }
 
-void variant_romstage_entry(int s3_resume)
+void variant_romstage_entry(void)
 {
 	uint32_t sku = google_chromeec_get_sku_id();
 	uint32_t bid;
 
-	if (!s3_resume) {
+	if (!acpi_is_wakeup_s3()) {
 		/* Based on SKU, turn on keyboard backlight */
 		switch (sku) {
 		default:

src/soc/amd/picasso/romstage.c

@@ -143,14 +143,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 
 asmlinkage void car_stage_entry(void)
 {
-	int s3_resume;
-
 	post_code(0x40);
 	console_init();
 
-	post_code(0x41);
-	s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();
-
 	post_code(0x42);
 	u32 val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
@@ -159,7 +154,7 @@ asmlinkage void car_stage_entry(void)
 	fill_chipset_state();
 
 	post_code(0x43);
-	fsp_memory_init(s3_resume);
+	fsp_memory_init(acpi_is_wakeup_s3());
 	soc_update_mrc_cache();
 
 	memmap_stash_early_dram_usage();

src/soc/amd/stoneyridge/chip.c

@@ -6,7 +6,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <drivers/i2c/designware/dw_i2c.h>
-#include <romstage_handoff.h>
 #include <soc/acpi.h>
 #include <soc/cpu.h>
 #include <soc/northbridge.h>
@@ -138,9 +137,7 @@ struct chip_operations soc_amd_stoneyridge_ops = {
 
 static void earliest_ramstage(void *unused)
 {
-	int s3_resume = acpi_s3_resume_allowed() &&
+	if (!acpi_is_wakeup_s3()) {
-			romstage_handoff_is_resume();
-	if (!s3_resume) {
 		post_code(0x46);
 		if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
 			psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2");

src/soc/amd/stoneyridge/include/soc/romstage.h

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_STONEYRIDGE_ROMSTAGE_H
-#define AMD_STONEYRIDGE_ROMSTAGE_H
-
-void mainboard_romstage_entry_s3(int s3_resume);
-
-#endif /* AMD_STONEYRIDGE_ROMSTAGE_H */

src/soc/amd/stoneyridge/northbridge.c

@@ -16,7 +16,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <romstage_handoff.h>
 #include <amdblocks/agesawrapper.h>
 #include <amdblocks/agesawrapper_call.h>
 #include <agesa_headers.h>
@@ -408,7 +407,7 @@ void fam15_finalize(void *chip_info)
 void domain_enable_resources(struct device *dev)
 {
 	/* Must be called after PCI enumeration and resource allocation */
-	if (!romstage_handoff_is_resume())
+	if (!acpi_is_wakeup_s3())
 		do_agesawrapper(AMD_INIT_MID, "amdinitmid");
 }
 

src/soc/amd/stoneyridge/romstage.c

@@ -20,13 +20,12 @@
 #include <amdblocks/agesawrapper_call.h>
 #include <soc/northbridge.h>
 #include <soc/pci_devs.h>
-#include <soc/romstage.h>
 #include <soc/southbridge.h>
 #include <amdblocks/psp.h>
 
 #include "chip.h"
 
-void __weak mainboard_romstage_entry_s3(int s3_resume)
+void __weak mainboard_romstage_entry(void)
 {
 	/* By default, don't do anything */
 }
@@ -54,7 +53,7 @@ asmlinkage void car_stage_entry(void)
 	msr_t base, mask;
 	msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
 	int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;
-	int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();
+	int s3_resume = acpi_is_wakeup_s3();
 	int i;
 
 	console_init();
@@ -63,7 +62,7 @@ asmlinkage void car_stage_entry(void)
 	if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
 		psp_load_named_blob(BLOB_SMU_FW, "smu_fw");
 
-	mainboard_romstage_entry_s3(s3_resume);
+	mainboard_romstage_entry();
 	elog_boot_notify(s3_resume);
 
 	bsp_agesa_call();