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mb/intel/mtlrvp: Enable PCIe port 7 for WWAN 

This patch enables PCIe port for WWAN as per mtlrvp schematics

BUG=b:224325352
BRANCH=None
TEST=Build and boot mtlrvp to ChromeOS. Ensure that WWAN module
gets enumerated with cbmem -c.

\_SB.PCI0.RP07: Enable RTD3 for PCI: 00:1c.6 (Intel PCIe Runtime D3)
\_SB.PCI0.RP07: Enable WWAN for PCI: 00:1c.6 (Fibocom FM-350-GL)

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ib372db9642a3c7b3a21a112fa0e6e0b4bc88a9ea
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72777
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Harsha B R 2023-02-04 10:32:20 +05:30 committed by Sridhar Siricilla
parent 1a832d0c06
commit 9e61ca5674
1 changed files with 8 additions and 0 deletions
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8
src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
View File

@ -79,6 +79,14 @@ chip soc/intel/meteorlake
device ref tcss_xhci on end device ref tcss_xhci on end
device ref tcss_dma0 on end device ref tcss_dma0 on end
device ref tcss_dma1 on end device ref tcss_dma1 on end
device ref pcie_rp7 on
# Enable PCH PCIE RP 7 using CLK 1
register "pcie_rp[PCIE_RP(7)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
}"
end # WWAN
device ref pcie_rp10 on device ref pcie_rp10 on
# Enable SSD Gen4 PCIE 10 using CLK 8 # Enable SSD Gen4 PCIE 10 using CLK 8
register "pcie_rp[PCIE_RP(10)]" = "{ register "pcie_rp[PCIE_RP(10)]" = "{