rockchip/rk3399: Clean up comments in sdram.c
Cleans up the comments in sdram.c to make them consistent. BRANCH=none BUG=none TEST=make sure gru/kevin build and boot also, run "stressapptest -M 1024 -s 3600" to make sure it passes Change-Id: I1daf72b847374d549389bacd2fa0a9f8f231b190 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 63a224d6f4b0e4d13bc372c05c4b9196895d553f Original-Change-Id: Iaf8a32cfe2b22c4ccff71952f90d162ad8c2d3e7 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/355665 Original-Reviewed-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15579 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Derek Basehore
Martin Roth
parent
58826fc85e
commit
9e624fc27f
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@ -119,8 +119,7 @@ static void phy_dll_bypass_set(u32 channel,
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struct rk3399_ddr_publ_regs *ddr_publ_regs, u32 freq)
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{
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if (freq <= 125*MHz) {
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/* phy_sw_master_mode_X */
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/* PHY_86/214/342/470 4bits offset_8 */
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/* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
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setbits_le32(&ddr_publ_regs->denali_phy[86],
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(0x3 << 2) << 8);
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setbits_le32(&ddr_publ_regs->denali_phy[214],
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@ -130,8 +129,7 @@ static void phy_dll_bypass_set(u32 channel,
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setbits_le32(&ddr_publ_regs->denali_phy[470],
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(0x3 << 2) << 8);
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/* phy_adrctl_sw_master_mode */
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/* PHY_547/675/803 4bits offset_16 */
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/* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
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setbits_le32(&ddr_publ_regs->denali_phy[547],
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(0x3 << 2) << 16);
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setbits_le32(&ddr_publ_regs->denali_phy[675],
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@ -139,8 +137,7 @@ static void phy_dll_bypass_set(u32 channel,
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setbits_le32(&ddr_publ_regs->denali_phy[803],
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(0x3 << 2) << 16);
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} else {
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/* phy_sw_master_mode_X */
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/* PHY_86/214/342/470 4bits offset_8 */
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/* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
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clrbits_le32(&ddr_publ_regs->denali_phy[86],
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(0x3 << 2) << 8);
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clrbits_le32(&ddr_publ_regs->denali_phy[214],
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@ -150,8 +147,7 @@ static void phy_dll_bypass_set(u32 channel,
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clrbits_le32(&ddr_publ_regs->denali_phy[470],
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(0x3 << 2) << 8);
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/* phy_adrctl_sw_master_mode */
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/* PHY_547/675/803 4bits offset_16 */
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/* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
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clrbits_le32(&ddr_publ_regs->denali_phy[547],
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(0x3 << 2) << 16);
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clrbits_le32(&ddr_publ_regs->denali_phy[675],
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@ -274,7 +270,7 @@ static void set_ds_odt(u32 channel,
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clrsetbits_le32(&ddr_publ_regs->denali_phy[672], 0xff, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[800], 0xff, reg_value);
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/* phy_pad_addr_drive 29bits DENALI_PHY_928 offset_0 */
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/* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
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clrsetbits_le32((&ddr_publ_regs->denali_phy[928]), 0xff, reg_value);
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/* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
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@ -329,6 +325,7 @@ static void set_ds_odt(u32 channel,
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clrsetbits_le32(&ddr_publ_regs->denali_phy[936], 0x1 << 17, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[940], 0x1 << 17, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[934], 0x1 << 17, reg_value);
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/* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
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clrsetbits_le32(&ddr_publ_regs->denali_phy[930], 0x1 << 17, reg_value);
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}
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@ -368,13 +365,11 @@ static void phy_io_config(u32 channel,
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clrsetbits_le32(&ddr_publ_regs->denali_phy[915], 0xfff << 16,
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reg_value << 16);
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/* mode setting */
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if (sdram_params->dramtype == LPDDR4)
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mode_sel = 0x6;
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else if (sdram_params->dramtype == LPDDR3)
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mode_sel = 0x0;
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else if (sdram_params->dramtype == DDR3)
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/* DDR3L */
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mode_sel = 0x1;
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/* PHY_924 PHY_PAD_FDBK_DRIVE */
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@ -402,7 +397,6 @@ static void phy_io_config(u32 channel,
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clrsetbits_le32(&ddr_publ_regs->denali_phy[939], 0x7 << 14,
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mode_sel << 14);
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/* SPEED */
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if (sdram_params->ddr_freq < 400 * MHz)
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speed = 0x0;
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else if (sdram_params->ddr_freq < 800 * MHz)
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@ -448,7 +442,8 @@ static void pctl_cfg(u32 channel,
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u32 tmp, tmp1, tmp2;
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u32 pwrup_srefresh_exit;
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/* workaround controller bug:
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/*
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* work around controller bug:
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* Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
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*/
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copy_to_reg(&ddr_pctl_regs->denali_ctl[1],
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@ -528,8 +523,10 @@ static void pctl_cfg(u32 channel,
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clrsetbits_le32(&ddr_publ_regs->denali_phy[468],
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0xff << 8, (tmp + 0x10) << 8);
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/* phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8 */
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/* dq_tsel_wr_end[7:4] add Half cycle */
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/*
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* phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
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* dq_tsel_wr_end[7:4] add Half cycle
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*/
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tmp = (read32(&ddr_publ_regs->denali_phy[83]) >> 16) & 0xff;
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clrsetbits_le32(&ddr_publ_regs->denali_phy[83],
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0xff << 16, (tmp + 0x10) << 16);
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@ -549,7 +546,8 @@ static void pctl_cfg(u32 channel,
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clrsetbits_le32(&ddr_publ_regs->denali_phy[957],
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0x3 << 24, 0x2 << 24);
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/* FIXME:
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/*
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* FIXME:
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* need to care ERROR bit
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*/
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while (!(read32(&ddr_pctl_regs->denali_ctl[203]) & (1 << 3)))
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@ -563,11 +561,12 @@ static void select_per_cs_training_index(u32 channel, u32 rank)
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{
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struct rk3399_ddr_publ_regs *ddr_publ_regs = rk3399_ddr_publ[channel];
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/*PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16*/
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/* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
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if ((read32(&ddr_publ_regs->denali_phy[84])>>16) & 1) {
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/*PHY_8/136/264/392
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*phy_per_cs_training_index_X 1bit offset_24
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*/
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/*
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* PHY_8/136/264/392
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* phy_per_cs_training_index_X 1bit offset_24
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*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[8],
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0x1 << 24, rank << 24);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[136],
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@ -738,8 +737,10 @@ static int data_training(u32 channel,
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while (1) {
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/* PI_174 PI_INT_STATUS:RD:8:18 */
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tmp = read32(&ddr_pi_regs->denali_pi[174]) >> 8;
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/* check status obs */
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/* PHY_532/660/789 phy_adr_calvl_obs1_:0:32 */
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/*
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* check status obs
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* PHY_532/660/789 phy_adr_calvl_obs1_:0:32
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*/
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obs_0 = read32(&ddr_publ_regs->denali_phy[532]);
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obs_1 = read32(&ddr_publ_regs->denali_phy[660]);
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obs_2 = read32(&ddr_publ_regs->denali_phy[789]);
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@ -775,7 +776,7 @@ static int data_training(u32 channel,
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select_per_cs_training_index(channel, i);
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while (1) {
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/*PI_174 PI_INT_STATUS:RD:8:18*/
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/* PI_174 PI_INT_STATUS:RD:8:18 */
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tmp = read32(&ddr_pi_regs->denali_pi[174]) >> 8;
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/*
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@ -816,8 +817,10 @@ static int data_training(u32 channel,
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clrsetbits_le32(&ddr_pi_regs->denali_pi[80],
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0x3 << 24,
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0x2 << 24);
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/* PI_74 PI_RDLVL_GATE_REQ:WR:16:1 */
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/* PI_RDLVL_CS:RW:24:2 */
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/*
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* PI_74 PI_RDLVL_GATE_REQ:WR:16:1
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* PI_RDLVL_CS:RW:24:2
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*/
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clrsetbits_le32(&ddr_pi_regs->denali_pi[74],
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(0x1 << 16) | (0x3 << 24),
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(0x1 << 16) | (i << 24));
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@ -826,7 +829,8 @@ static int data_training(u32 channel,
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while (1) {
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/* PI_174 PI_INT_STATUS:RD:8:18 */
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tmp = read32(&ddr_pi_regs->denali_pi[174]) >> 8;
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/* check status obs
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/*
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* check status obs
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* PHY_43/171/299/427
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* PHY_GTLVL_STATUS_OBS_x:16:8
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*/
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@ -869,7 +873,8 @@ static int data_training(u32 channel,
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while (1) {
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/* PI_174 PI_INT_STATUS:RD:8:18 */
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tmp = read32(&ddr_pi_regs->denali_pi[174]) >> 8;
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/* make sure status obs not report error bit
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/*
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* make sure status obs not report error bit
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* PHY_46/174/302/430
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* phy_rdlvl_status_obs_X:16:8
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*/
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@ -888,8 +893,10 @@ static int data_training(u32 channel,
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/* wdq leveling(LPDDR4 support) */
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if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
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for (i = 0; i < rank; i++) {
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/* disable PI_WDQLVL_VREF_EN before wdq leveling? */
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/* PI_181 PI_WDQLVL_VREF_EN:RW:8:1 */
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/*
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* disable PI_WDQLVL_VREF_EN before wdq leveling?
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* PI_181 PI_WDQLVL_VREF_EN:RW:8:1
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*/
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clrbits_le32(&ddr_pi_regs->denali_pi[181], 0x1 << 8);
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/* PI_124 PI_WDQLVL_EN:RW:16:2 */
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clrsetbits_le32(&ddr_pi_regs->denali_pi[124],
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