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soc/intel/broadwell: use common Intel ACPI hardware definitions

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Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.

BUG=chrome-os-partner:54977

Change-Id: I99d909ee72c3abebb1e9c8ebf44137465264bf0d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15673
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin 2016-07-13 23:21:41 -05:00
parent c159bb0d76
commit 9e6d143a82
9 changed files with 32 additions and 41 deletions
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1
src/soc/intel/broadwell/Kconfig
View file

@ -7,6 +7,7 @@ if SOC_INTEL_BROADWELL
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32

4
src/soc/intel/broadwell/elog.c
View file

@ -92,7 +92,7 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps)
elog_add_event(ELOG_TYPE_PWROK_FAIL);
/* TCO Timeout */
if (ps->prev_sleep_state != 3 &&
if (ps->prev_sleep_state != ACPI_S3 &&
ps->tco2_sts & TCO2_STS_SECOND_TO)
elog_add_event(ELOG_TYPE_TCO_RESET);
@ -113,7 +113,7 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps)
elog_add_event(ELOG_TYPE_SYSTEM_RESET);
/* ACPI Wake Event */
if (ps->prev_sleep_state != SLEEP_STATE_S0)
if (ps->prev_sleep_state != ACPI_S0)
elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state);
}

14
src/soc/intel/broadwell/include/soc/pm.h
View file

@ -16,6 +16,8 @@
#ifndef _BROADWELL_PM_H_
#define _BROADWELL_PM_H_
#include <arch/acpi.h>
/* ACPI_BASE_ADDRESS / PMBASE */
#define PM1_STS 0x00
@ -34,14 +36,6 @@
#define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0)
#define PM1_CNT 0x04
#define SLP_EN (1 << 13)
#define SLP_TYP (7 << 10)
#define SLP_TYP_SHIFT 10
#define SLP_TYP_S0 0
#define SLP_TYP_S1 1
#define SLP_TYP_S3 5
#define SLP_TYP_S4 6
#define SLP_TYP_S5 7
#define GBL_RLS (1 << 2)
#define BM_RLD (1 << 1)
#define SCI_EN (1 << 0)
@ -113,10 +107,6 @@
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
#define SLEEP_STATE_S0 0
#define SLEEP_STATE_S3 3
#define SLEEP_STATE_S5 5
struct chipset_power_state {
uint16_t pm1_sts;
uint16_t pm1_en;

2
src/soc/intel/broadwell/refcode.c
View file

@ -78,7 +78,7 @@ void broadwell_run_reference_code(void)
mainboard_fill_pei_data(&pei_data);
broadwell_fill_pei_data(&pei_data);
pei_data.boot_mode = acpi_is_wakeup_s3() ? SLEEP_STATE_S3 : 0;
pei_data.boot_mode = acpi_is_wakeup_s3() ? ACPI_S3 : 0;
pei_data.saved_data = (void *) &dummy;
entry = load_reference_code();

17
src/soc/intel/broadwell/romstage/power_state.c
View file

@ -52,17 +52,16 @@ ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state)
static int prev_sleep_state(struct chipset_power_state *ps)
{
/* Default to S0. */
int prev_sleep_state = SLEEP_STATE_S0;
int prev_sleep_state = ACPI_S0;
if (ps->pm1_sts & WAK_STS) {
switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
#if CONFIG_HAVE_ACPI_RESUME
case SLP_TYP_S3:
prev_sleep_state = SLEEP_STATE_S3;
switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
case ACPI_S3:
if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
prev_sleep_state = ACPI_S3;
break;
#endif
case SLP_TYP_S5:
prev_sleep_state = SLEEP_STATE_S5;
case ACPI_S5:
prev_sleep_state = ACPI_S5;
break;
}
/* Clear SLP_TYP. */
@ -70,7 +69,7 @@ static int prev_sleep_state(struct chipset_power_state *ps)
}
if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR))
prev_sleep_state = SLEEP_STATE_S5;
prev_sleep_state = ACPI_S5;
return prev_sleep_state;
}

6
src/soc/intel/broadwell/romstage/raminit.c
View file

@ -55,7 +55,7 @@ void raminit(struct pei_data *pei_data)
/* MRC cache found */
pei_data->saved_data_size = cache->size;
pei_data->saved_data = &cache->data[0];
} else if (pei_data->boot_mode == SLEEP_STATE_S3) {
} else if (pei_data->boot_mode == ACPI_S3) {
/* Waking from S3 and no cache. */
printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
post_code(POST_RESUME_FAILURE);
@ -63,7 +63,7 @@ void raminit(struct pei_data *pei_data)
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
#if CONFIG_EC_GOOGLE_CHROMEEC
if (pei_data->boot_mode == SLEEP_STATE_S0) {
if (pei_data->boot_mode == ACPI_S0) {
/* Ensure EC is running RO firmware. */
google_chromeec_check_ec_image(EC_IMAGE_RO);
}
@ -104,7 +104,7 @@ void raminit(struct pei_data *pei_data)
/* Basic memory sanity test */
quick_ram_check();
if (pei_data->boot_mode != SLEEP_STATE_S3) {
if (pei_data->boot_mode != ACPI_S3) {
cbmem_initialize_empty();
} else if (cbmem_initialize()) {
#if CONFIG_HAVE_ACPI_RESUME

6
src/soc/intel/broadwell/romstage/romstage.c
View file

@ -98,7 +98,7 @@ void romstage_common(struct romstage_params *params)
params->pei_data->boot_mode = params->power_state->prev_sleep_state;
#if CONFIG_ELOG_BOOT_COUNT
if (params->power_state->prev_sleep_state != SLEEP_STATE_S3)
if (params->power_state->prev_sleep_state != ACPI_S3)
boot_count_increment();
#endif
@ -117,12 +117,12 @@ void romstage_common(struct romstage_params *params)
handoff = romstage_handoff_find_or_add();
if (handoff != NULL)
handoff->s3_resume = (params->power_state->prev_sleep_state ==
SLEEP_STATE_S3);
ACPI_S3);
else
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
#if CONFIG_LPC_TPM
init_tpm(params->power_state->prev_sleep_state == SLEEP_STATE_S3);
init_tpm(params->power_state->prev_sleep_state == ACPI_S3);
#endif
}

20
src/soc/intel/broadwell/smihandler.c
View file

@ -167,18 +167,18 @@ static void southbridge_smi_sleep(void)
/* Figure out SLP_TYP */
reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);
printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
slp_typ = (reg32 >> 10) & 7;
slp_typ = acpi_sleep_from_pm1(reg32);
/* Do any mainboard sleep handling */
mainboard_smi_sleep(slp_typ-2);
mainboard_smi_sleep(slp_typ);
/* USB sleep preparations */
usb_xhci_sleep_prepare(PCH_DEV_XHCI, slp_typ);
#if CONFIG_ELOG_GSMI
/* Log S3, S4, and S5 entry */
if (slp_typ >= 5)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2);
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
#endif
/* Clear pending GPE events */
@ -188,22 +188,22 @@ static void southbridge_smi_sleep(void)
*/
switch (slp_typ) {
case SLP_TYP_S0:
case ACPI_S0:
printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
break;
case SLP_TYP_S1:
case ACPI_S1:
printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n");
break;
case SLP_TYP_S3:
case ACPI_S3:
printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
/* Invalidate the cache before going to S3 */
wbinvd();
break;
case SLP_TYP_S4:
case ACPI_S4:
printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n");
break;
case SLP_TYP_S5:
case ACPI_S5:
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
/* Turn off backlight if needed */
@ -238,7 +238,7 @@ static void southbridge_smi_sleep(void)
enable_pm1_control(SLP_EN);
/* Make sure to stop executing code here for S3/S4/S5 */
if (slp_typ > 1)
if (slp_typ >= ACPI_S3)
halt();
/*

3
src/soc/intel/broadwell/xhci.c
View file

@ -18,6 +18,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <soc/ramstage.h>
#include <soc/xhci.h>
@ -146,7 +147,7 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
u8 *mem_base = usb_xhci_mem_base(dev);
u8 is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
if (!mem_base || slp_typ < 3)
if (!mem_base || slp_typ < ACPI_S3)
return;
/* Set D0 state */