mb/google/dedede: Update EC_MKBP_INT_L configuration
The concerned GPIO is configured as an open drain at the Embedded Controller side without an external pull-up. This causes leakage in the PP3300_A rail. So configure the GPIO to have a weak internal pull-up at the SoC side. BUG=b:151680590 TEST=Build the mainboard. Ensure that there are no leakages in the PP3300_A rail. Change-Id: I5553cf40adb92edc0fecab5c875ec8d72063ba7b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -127,7 +127,7 @@ static const struct pad_config gpio_table[] = {
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/* C14 : EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_C14, NONE, DEEP),
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/* C15 : EC_AP_MKBP_INT_L */
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PAD_CFG_GPI_APIC(GPP_C15, NONE, PLTRST, LEVEL, INVERT),
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PAD_CFG_GPI_APIC(GPP_C15, UP_20K, PLTRST, LEVEL, INVERT),
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/* C16 : AP_I2C_TRACKPAD_SDA_3V3 */
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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/* C17 : AP_I2C_TRACKPAD_SCL_3V3 */
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