Inagua: devicetree.cb update
Add the slots connection comments to devicetree.cb Change-Id: I3ccb2641c8d04a6a3c66ac11a562ba3b0dc0578a Signed-off-by: Kerry Sheh <shekairui@gmail.com> Signed-off-by: Kerry Sheh <kerry.she@amd.com> Reviewed-on: http://review.coreboot.org/545 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
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@ -30,10 +30,10 @@ chip northbridge/amd/agesa/family14/root_complex
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device pci 0.0 on end # Root Complex
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device pci 0.0 on end # Root Complex
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device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806
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device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806
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device pci 1.1 on end # Internal Multimedia
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device pci 1.1 on end # Internal Multimedia
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device pci 4.0 on end # PCIE P2P bridge 0x9604
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device pci 4.0 on end # PCIE P2P bridge MXM lane 0
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device pci 5.0 off end # PCIE P2P bridge 0x9605
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device pci 5.0 off end # PCIE P2P bridge MXM lane 1
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device pci 6.0 on end # PCIE P2P bridge 0x9606
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device pci 6.0 on end # PCIE P2P bridge LAN
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device pci 7.0 off end # PCIE P2P bridge 0x9607
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device pci 7.0 on end # PCIE P2P bridge MINIPCIE SLOT1
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device pci 8.0 off end # NB/SB Link P2P bridge
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device pci 8.0 off end # NB/SB Link P2P bridge
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end # agesa northbridge
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end # agesa northbridge
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@ -67,10 +67,10 @@ chip northbridge/amd/agesa/family14/root_complex
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end #LPC
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end #LPC
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device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
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device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
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device pci 14.5 on end # USB 2
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device pci 14.5 on end # USB 2
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device pci 15.0 on end # PCIe PortA
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device pci 15.0 on end # PCIe PortA Express Card
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device pci 15.1 on end # PCIe PortB
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device pci 15.1 on end # PCIe PortB NEC USB3.0
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device pci 15.2 on end # PCIe PortC
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device pci 15.2 on end # PCIe PortC MINIPCIE SLOT2
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device pci 15.3 on end # PCIe PortD
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device pci 15.3 on end # PCIe PortD PCIE X1 SLOT
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device pci 16.0 on end # OHCI USB3
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device pci 16.0 on end # OHCI USB3
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device pci 16.2 on end # EHCI USB3
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device pci 16.2 on end # EHCI USB3
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register "gpp_configuration" = "4" #1:1:1:1
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register "gpp_configuration" = "4" #1:1:1:1
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