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mb/google/volteer: Add delay to WWAN GPIO init sequence 

Based on Fibocom HW user manual RESET should be deasserted at least 20ms after the power on pin.
The design for the reset pin is open drain connected to a pull up, so it is set to high-Z (configured as GPIO in) after 20ms.

BUG=b:152013143
BRANCH=none
TEST=traced the signals using a scope to verify timing is met.

Signed-off-by: Alex Levin <levinale@chromium.org>
Change-Id: I7c947d1bc4cce1f97383a2f2c254986e182661c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41356
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Alex Levin 2020-05-12 21:24:23 -07:00 committed by Aaron Durbin
parent ecc4c4e5f1
commit 9e8dd06cd4
1 changed files with 9 additions and 3 deletions
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12
src/mainboard/google/volteer/variants/baseboard/gpio.c
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@ -265,10 +265,8 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_F9, NONE),
/* F10 : GPPF10_STRAP */
PAD_NC(GPP_F10, DN_20K),
/* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */
PAD_CFG_GPO(GPP_F11, 1, DEEP),
/* F12 : GSXDOUT ==> WWAN_RST_ODL */
PAD_CFG_GPO(GPP_F12, 1, DEEP),
PAD_CFG_GPI(GPP_F12, NONE, DEEP),
/* F13 : GSXDOUT ==> WiFi_DISABLE_L */
PAD_CFG_GPO(GPP_F13, 1, DEEP),
/* F14 : GSXDIN ==> SAR0_INT_L */
@ -435,6 +433,14 @@ static const struct pad_config early_gpio_table[] = {
/* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_E12, 1, DEEP),
/* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */
PAD_CFG_GPO(GPP_F11, 1, DEEP),
/* F12 : GSXDOUT ==> WWAN_RST_ODL
To meet timing constrains - drive reset low.
Deasserted in ramstage. */
PAD_CFG_GPO(GPP_F12, 0, DEEP),
/* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
PAD_CFG_GPO(GPP_H11, 1, DEEP),
};