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ACPI: Get S3 resume state from romstage_handoff 

There is nothing platform specific in retrieving S3 resume state from
romstage_handoff structure. Boards without EARLY_CBMEM_INIT update
acpi_slp_type from ACPI power-management block or scratchpad registers.

Change-Id: Ifc3755f891a0810473b3216c1fec8e45908fc1ab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8188
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Kyösti Mälkki 2015-01-08 20:03:18 +02:00
parent a63719407f
commit 9e94dbfcd0
12 changed files with 45 additions and 128 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/arch/x86/boot/acpi.c
View File

@ -36,6 +36,7 @@
#if CONFIG_COLLECT_TIMESTAMPS
#include <timestamp.h>
#endif
#include <romstage_handoff.h>
/* FIXME: Kconfig doesn't support overridable defaults :-( */
#ifndef CONFIG_HPET_MIN_TICKS
@ -857,10 +858,25 @@ void acpi_resume(void *wake_vec)
/* This is filled with acpi_is_wakeup() call early in ramstage. */
int acpi_slp_type = -1;
int __attribute__((weak)) acpi_get_sleep_type(void)
#if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)
int acpi_get_sleep_type(void)
{
struct romstage_handoff *handoff;
handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
if (handoff == NULL) {
printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
return 0;
} else if (handoff->s3_resume) {
printk(BIOS_DEBUG, "S3 Resume.\n");
return 3;
} else {
printk(BIOS_DEBUG, "Normal boot.\n");
return 0;
}
}
#endif
static void acpi_handoff_wakeup(void)
{

22
src/northbridge/intel/haswell/northbridge.c
View File

@ -35,7 +35,6 @@
#include <cpu/x86/smm.h>
#include <boot/tables.h>
#include <cbmem.h>
#include <romstage_handoff.h>
#include "chip.h"
#include "haswell.h"
@ -433,26 +432,6 @@ static void northbridge_init(struct device *dev)
MCHBAR32(0x5500) = 0x00100001;
}
static void northbridge_enable(device_t dev)
{
#if CONFIG_HAVE_ACPI_RESUME
struct romstage_handoff *handoff;
handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
if (handoff == NULL) {
printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
acpi_slp_type = 0;
} else if (handoff->s3_resume) {
printk(BIOS_DEBUG, "S3 Resume.\n");
acpi_slp_type = 3;
} else {
printk(BIOS_DEBUG, "Normal boot.\n");
acpi_slp_type = 0;
}
#endif
}
static struct pci_operations intel_pci_ops = {
.set_subsystem = intel_set_subsystem,
};
@ -462,7 +441,6 @@ static struct device_operations mc_ops = {
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = northbridge_init,
.enable = northbridge_enable,
.acpi_fill_ssdt_generator = generate_cpu_entries,
.scan_bus = 0,
.ops_pci = &intel_pci_ops,

24
src/soc/intel/baytrail/ramstage.c
View File

@ -27,8 +27,8 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <romstage_handoff.h>
#include <stdlib.h>
#include <string.h>
#include <baytrail/gpio.h>
#include <baytrail/lpc.h>
@ -130,13 +130,6 @@ static void fill_in_pattrs(void)
attrs->bclk_khz = bus_freq_khz();
}
static inline void set_acpi_sleep_type(int val)
{
#if CONFIG_HAVE_ACPI_RESUME
acpi_slp_type = val;
#endif
}
/* Save bit index for first enabled event in PM1_STS for \_SB._SWS */
static void s3_save_acpi_wake_source(global_nvs_t *gnvs)
{
@ -166,21 +159,14 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs)
static void s3_resume_prepare(void)
{
global_nvs_t *gnvs;
struct romstage_handoff *romstage_handoff;
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) {
if (gnvs != NULL) {
memset(gnvs, 0, sizeof(global_nvs_t));
}
set_acpi_sleep_type(0);
if (gnvs == NULL)
return;
}
set_acpi_sleep_type(3);
if (!acpi_is_wakeup_s3())
memset(gnvs, 0, sizeof(global_nvs_t));
else
s3_save_acpi_wake_source(gnvs);
}

3
src/soc/intel/baytrail/southcluster.c
View File

@ -29,7 +29,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <pc80/mc146818rtc.h>
#include <romstage_handoff.h>
#include <drivers/uart/uart8250reg.h>
#include <baytrail/iomap.h>
@ -215,7 +214,7 @@ static void sc_init(device_t dev)
read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP);
}
if (acpi_slp_type == 3)
if (acpi_is_wakeup_s3())
com1_configure_resume(dev);
}

4
src/soc/intel/baytrail/xhci.c
View File

@ -184,7 +184,7 @@ static void xhci_route_all(device_t dev)
/* Route ports to XHCI controller */
reg_script_run_on_dev(dev, xhci_route_all_script);
if (acpi_slp_type == 3)
if (acpi_is_wakeup_s3())
return;
/* Reset enabled USB3 ports */
@ -222,7 +222,7 @@ static void xhci_init(device_t dev)
};
/* Initialize XHCI controller for boot or resume path */
if (acpi_slp_type == 3)
if (acpi_is_wakeup_s3())
reg_script_run_on_dev(dev, xhci_init_resume_script);
else
reg_script_run_on_dev(dev, xhci_init_boot_script);

4
src/soc/intel/broadwell/lpc.c
View File

@ -394,7 +394,7 @@ static void pch_cg_init(device_t dev)
static void pch_set_acpi_mode(void)
{
#if CONFIG_HAVE_SMI_HANDLER
if (acpi_slp_type != 3) {
if (!acpi_is_wakeup_s3()) {
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_DISABLE, APM_CNT);
printk(BIOS_DEBUG, "done.\n");
@ -551,7 +551,7 @@ static void pch_lpc_read_resources(device_t dev)
/* Allocate ACPI NVS in CBMEM */
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
if (acpi_slp_type != 3 && gnvs)
if (!acpi_is_wakeup_s3() && gnvs)
memset(gnvs, 0, sizeof(global_nvs_t));
}

4
src/soc/intel/broadwell/me.c
View File

@ -830,13 +830,11 @@ static void intel_me_init(device_t dev)
static void intel_me_enable(device_t dev)
{
#if CONFIG_HAVE_ACPI_RESUME
/* Avoid talking to the device in S3 path */
if (acpi_slp_type == 3) {
if (acpi_is_wakeup_s3()) {
dev->enabled = 0;
pch_disable_devfn(dev);
}
#endif
}
static struct device_operations device_ops = {

23
src/soc/intel/broadwell/ramstage.c
View File

@ -21,8 +21,8 @@
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
#include <romstage_handoff.h>
#include <stdlib.h>
#include <string.h>
#include <broadwell/nvs.h>
#include <broadwell/pm.h>
#include <broadwell/ramstage.h>
@ -54,30 +54,17 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs)
gnvs->pm1i);
}
static inline void set_acpi_sleep_type(int val)
{
#if CONFIG_HAVE_ACPI_RESUME
acpi_slp_type = val;
#endif
}
static void s3_resume_prepare(void)
{
global_nvs_t *gnvs;
struct romstage_handoff *romstage_handoff;
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) {
if (gnvs != NULL) {
memset(gnvs, 0, sizeof(global_nvs_t));
}
set_acpi_sleep_type(0);
if (gnvs == NULL)
return;
}
set_acpi_sleep_type(3);
if (!acpi_is_wakeup_s3())
memset(gnvs, 0, sizeof(global_nvs_t));
else
s3_save_acpi_wake_source(gnvs);
}

11
src/soc/intel/broadwell/refcode.c
View File

@ -30,15 +30,6 @@
#include <broadwell/pei_wrapper.h>
#include <broadwell/ramstage.h>
static inline int is_s3_resume(void)
{
#if CONFIG_HAVE_ACPI_RESUME
return acpi_slp_type == 3;
#else
return 0;
#endif
}
static inline struct ramstage_cache *next_cache(struct ramstage_cache *c)
{
return (struct ramstage_cache *)&c->program[c->size];
@ -136,7 +127,7 @@ static pei_wrapper_entry_t load_reference_code(void)
};
int ret;
if (is_s3_resume()) {
if (acpi_is_wakeup_s3()) {
return load_refcode_from_cache();
}

23
src/soc/intel/broadwell/systemagent.c
View File

@ -29,7 +29,6 @@
#include <stdlib.h>
#include <string.h>
#include <cbmem.h>
#include <romstage_handoff.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <broadwell/cpu.h>
#include <broadwell/iomap.h>
@ -412,27 +411,6 @@ static void systemagent_init(struct device *dev)
set_power_limits(28);
}
static void systemagent_enable(device_t dev)
{
#if CONFIG_HAVE_ACPI_RESUME
struct romstage_handoff *handoff;
handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
if (handoff == NULL) {
printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
acpi_slp_type = 0;
} else if (handoff->s3_resume) {
printk(BIOS_DEBUG, "S3 Resume.\n");
acpi_slp_type = 3;
} else {
printk(BIOS_DEBUG, "Normal boot.\n");
acpi_slp_type = 0;
}
#endif
}
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
@ -451,7 +429,6 @@ static struct device_operations systemagent_ops = {
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.init = &systemagent_init,
.enable = &systemagent_enable,
.ops_pci = &broadwell_pci_ops,
};

24
src/soc/intel/fsp_baytrail/ramstage.c
View File

@ -19,6 +19,7 @@
#include <arch/cpu.h>
#include <arch/acpi.h>
#include <cbmem.h>
#include <console/console.h>
#include <cpu/intel/microcode.h>
#include <cpu/x86/cr.h>
@ -26,8 +27,8 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <romstage_handoff.h>
#include <stdlib.h>
#include <string.h>
#include <baytrail/gpio.h>
#include <baytrail/lpc.h>
@ -125,31 +126,16 @@ static void fill_in_pattrs(void)
attrs->bclk_khz = bus_freq_khz();
}
static inline void set_acpi_sleep_type(int val)
{
#if CONFIG_HAVE_ACPI_RESUME
acpi_slp_type = val;
#endif
}
static void s3_resume_prepare(void)
{
global_nvs_t *gnvs;
struct romstage_handoff *romstage_handoff;
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) {
if (gnvs != NULL) {
memset(gnvs, 0, sizeof(global_nvs_t));
}
set_acpi_sleep_type(0);
if (gnvs == NULL)
return;
}
set_acpi_sleep_type(3);
if (!acpi_is_wakeup_s3())
memset(gnvs, 0, sizeof(global_nvs_t));
}
void baytrail_init_pre_device(void)

1
src/soc/intel/fsp_baytrail/southcluster.c
View File

@ -33,7 +33,6 @@
#include <pc80/i8254.h>
#include <pc80/i8259.h>
#include <pc80/isa-dma.h>
#include <romstage_handoff.h>
#include <baytrail/baytrail.h>
#include <baytrail/iomap.h>