intel/i5000: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on two boards with i5000 chipset. To enable MMIO style access, add explicit PCI IO config write in the bootblock. Change-Id: I26f1c2da5ae98aeeda78bdcae0fb1e8c711a3586 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3601 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -129,10 +129,6 @@ void main(unsigned long bist)
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enable_smbus();
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/* setup PCIe MMCONF base address */
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pci_write_config32(PCI_DEV(0, 16, 0), 0x64,
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CONFIG_MMCONF_BASE_ADDRESS >> 16);
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smbus_write_byte(0x6f, 0x00, 0x63);
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smbus_write_byte(0x6f, 0x01, 0x04);
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smbus_write_byte(0x6f, 0x02, 0x53);
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@ -128,10 +128,6 @@ void main(unsigned long bist)
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enable_smbus();
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/* setup PCIe MMCONF base address */
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pci_write_config32(PCI_DEV(0, 16, 0), 0x64,
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CONFIG_MMCONF_BASE_ADDRESS >> 16);
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outb(0x07, 0x11b8);
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/* These are smbus write captured with serialice. They
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@ -20,9 +20,17 @@
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config NORTHBRIDGE_INTEL_I5000
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bool
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select MMCONF_SUPPORT
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select MMCONF_SUPPORT_DEFAULT
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select HAVE_DEBUG_RAM_SETUP
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if NORTHBRIDGE_INTEL_I5000
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config NORTHBRIDGE_INTEL_I5000_RAM_CHECK
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bool
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prompt "Run ramcheck after RAM initialization"
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depends on NORTHBRIDGE_INTEL_I5000
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config BOOTBLOCK_NORTHBRIDGE_INIT
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string
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default "northbridge/intel/i5000/bootblock.c"
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endif
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@ -0,0 +1,21 @@
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#include <arch/io.h>
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static void bootblock_northbridge_init(void)
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{
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/*
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* The "io" variant of the config access is explicitly used to
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* setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
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* to true. That way all subsequent non-explicit config accesses use
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* MCFG. This code also assumes that bootblock_northbridge_init() is
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* the first thing called in the non-asm boot block code. The final
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* assumption is that no assembly code is using the
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* CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
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*
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* The PCIEXBAR is assumed to live in the memory mapped IO space under
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* 4GiB.
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*/
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/* setup PCIe MMCONF base address */
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pci_io_write_config32(PCI_DEV(0, 16, 0), 0x64,
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CONFIG_MMCONF_BASE_ADDRESS >> 16);
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}
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