intel/i5000: Use MMCONF_SUPPORT_DEFAULT

Change all PCI configuration accesses to MMIO on two boards
with i5000 chipset. To enable MMIO style access, add explicit
PCI IO config write in the bootblock.

Change-Id: I26f1c2da5ae98aeeda78bdcae0fb1e8c711a3586
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3601
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Kyösti Mälkki 2013-07-01 11:21:53 +03:00 committed by Ronald G. Minnich
parent 575e6817e6
commit 9e974232e4
4 changed files with 30 additions and 9 deletions

View File

@ -129,10 +129,6 @@ void main(unsigned long bist)
enable_smbus();
/* setup PCIe MMCONF base address */
pci_write_config32(PCI_DEV(0, 16, 0), 0x64,
CONFIG_MMCONF_BASE_ADDRESS >> 16);
smbus_write_byte(0x6f, 0x00, 0x63);
smbus_write_byte(0x6f, 0x01, 0x04);
smbus_write_byte(0x6f, 0x02, 0x53);

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@ -128,10 +128,6 @@ void main(unsigned long bist)
enable_smbus();
/* setup PCIe MMCONF base address */
pci_write_config32(PCI_DEV(0, 16, 0), 0x64,
CONFIG_MMCONF_BASE_ADDRESS >> 16);
outb(0x07, 0x11b8);
/* These are smbus write captured with serialice. They

View File

@ -20,9 +20,17 @@
config NORTHBRIDGE_INTEL_I5000
bool
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select HAVE_DEBUG_RAM_SETUP
if NORTHBRIDGE_INTEL_I5000
config NORTHBRIDGE_INTEL_I5000_RAM_CHECK
bool
prompt "Run ramcheck after RAM initialization"
depends on NORTHBRIDGE_INTEL_I5000
config BOOTBLOCK_NORTHBRIDGE_INIT
string
default "northbridge/intel/i5000/bootblock.c"
endif

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@ -0,0 +1,21 @@
#include <arch/io.h>
static void bootblock_northbridge_init(void)
{
/*
* The "io" variant of the config access is explicitly used to
* setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
* to true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
* CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
*/
/* setup PCIe MMCONF base address */
pci_io_write_config32(PCI_DEV(0, 16, 0), 0x64,
CONFIG_MMCONF_BASE_ADDRESS >> 16);
}