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soc/intel/apollolake: Enable decoding for ComA and ComB on LPC 

If there is an external 8250 UART, one needs to enable the appropriate
address ranges before console_init() is called so that the init sequence
can reach the external UART.

Furthermore FSPM needs different settings for an external UART port. For
this, the function fill_console_params() has to be adapted.

Change-Id: I62c7d0b54edd18acf793849aef352afbcaeb68b9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/19693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Mario Scheithauer 2017-05-15 17:24:56 +02:00 committed by Werner Zeh
parent c5eab98e78
commit 9e9cf270c4
2 changed files with 37 additions and 9 deletions
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5
src/soc/intel/apollolake/include/soc/lpc.h
View File

@ -29,8 +29,11 @@
* IO decode enable macros are in the format IO_<peripheral>_<IO port>.
* For example, to open ports 0x60, 0x64 for the keyboard controller,
* use IOE_KBC_60_64 macro. For IOE_ macros that do not specify a port range,
* the port range is selectable via the IO decodes register (not referenced).
* the port range is selectable via the IO decodes register.
*/
#define REG_IO_DECODE 0x80
#define IOD_COMA_RANGE (0 << 0) /* 0x3F8 - 0x3FF COMA*/
#define IOD_COMB_RANGE (1 << 4) /* 0x2F8 - 0x2FF COMB*/
#define REG_IO_ENABLES 0x82
#define IOE_EC_4E_4F (1 << 13)
#define IOE_SUPERIO_2E_2F (1 << 12)

41
src/soc/intel/apollolake/romstage.c
View File

@ -35,6 +35,7 @@
#include <soc/cpu.h>
#include <soc/intel/common/mrc_cache.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/systemagent.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
@ -85,6 +86,18 @@ static void soc_early_romstage_init(void)
/* Enable decoding for HPET. Needed for FSP global pointer storage */
pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
P2SB_HPTC_ADDRESS_ENABLE);
if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) {
/*
* I/O Decode Range Register for LPC
* ComA Range 3F8h-3FFh [2:0]
* ComB Range 2F8h-2FFh [6:4]
*/
pci_write_config16(PCH_DEV_LPC, REG_IO_DECODE,
IOD_COMA_RANGE | IOD_COMB_RANGE);
/* Enable ComA and ComB Port */
lpc_enable_fixed_io_ranges(IOE_COMA_EN | IOE_COMB_EN);
}
}
static void disable_watchdog(void)
@ -245,14 +258,26 @@ asmlinkage void car_stage_entry(void)
static void fill_console_params(FSPM_UPD *mupd)
{
if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
mupd->FspmConfig.SerialDebugPortDevice =
CONFIG_UART_FOR_CONSOLE;
/* use MMIO port type */
mupd->FspmConfig.SerialDebugPortType = 2;
/* use 4 byte register stride */
mupd->FspmConfig.SerialDebugPortStrideSize = 2;
/* used only for port type set to external */
mupd->FspmConfig.SerialDebugPortAddress = 0;
if (IS_ENABLED(CONFIG_SOC_UART_DEBUG)) {
mupd->FspmConfig.SerialDebugPortDevice =
CONFIG_UART_FOR_CONSOLE;
/* use MMIO port type */
mupd->FspmConfig.SerialDebugPortType = 2;
/* use 4 byte register stride */
mupd->FspmConfig.SerialDebugPortStrideSize = 2;
/* used only for port type set to external */
mupd->FspmConfig.SerialDebugPortAddress = 0;
} else if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) {
/* use external UART for debug */
mupd->FspmConfig.SerialDebugPortDevice = 3;
/* use I/O port type */
mupd->FspmConfig.SerialDebugPortType = 1;
/* use 1 byte register stride */
mupd->FspmConfig.SerialDebugPortStrideSize = 0;
/* used only for port type set to external */
mupd->FspmConfig.SerialDebugPortAddress =
CONFIG_TTYS0_BASE;
}
} else {
mupd->FspmConfig.SerialDebugPortType = 0;
}