soc/intel/tigerlake: Fix wrong operation region for CPU to PCH method
CPU to PCH method refers to PCH ACPI operation region which was wrongly defined as SystemIO. This causes ACPI AE_LIMIT error from PM _DSW method. Change the operation region from SystemIO to SystemMemory to resolve this execution failure. BUG=b:140290596 TEST=Built and booted to kernel. _DSW method executes successfully without ACPI AE_LIMIT error. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I3965c3d891f7d3cf4a448edc0c3f7e7749a905a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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@ -45,10 +45,10 @@ Scope (\_SB)
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}
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/*
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* Define PCH ACPIBASE I/O as an ACPI operating region. The base address can be
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* Define PCH ACPIBASE as an ACPI operating region. The base address can be
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* found in Device 31, Function 2, Offset 40h.
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*/
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OperationRegion (PMIO, SystemIO, PCH_PWRM_BASE_ADDRESS, 0x80)
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OperationRegion (PMIO, SystemMemory, PCH_PWRM_BASE_ADDRESS, 0x80)
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Field (PMIO, ByteAcc, NoLock, Preserve) {
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Offset(0x6C), /* 0x6C, General Purpose Event 0 Status [127:96] */
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, 19,
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@ -74,7 +74,7 @@ Scope (\_SB)
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*/
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Method (C2PM, 4, NotSerialized)
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{
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Local0 = 0x1 << Arg3
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Local0 = 1 << Arg3
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/* This method is used to enable/disable wake from Tcss Device (WKEN). */
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If (Arg0 && Arg1)
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{ /* If entering Sx and enabling wake, need to enable WAKE capability. */
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@ -64,7 +64,7 @@ Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
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*/
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Method (_DSM, 4, Serialized)
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{
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return (Buffer() {0x00})
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Return (Buffer() {0x00})
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}
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Device (PXSX)
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