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intel/cannonlake: Implement PCIe RP devicetree update 

Some existing devicetrees were manually adapted to anticipate
root-port switching. Now, their PCI-device on/off settings should
just reflect the `PcieRpEnable` state and configuration happens
on the PCI function that was assigned at reset.

Change-Id: I4d76f38c222b74053c6a2f80b492d4660ab4db6d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Nico Huber 2019-10-12 15:16:33 +02:00 committed by Patrick Georgi
parent 95dcf29b2f
commit 9ea70c02cd
6 changed files with 30 additions and 13 deletions
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5
src/mainboard/google/hatch/variants/duffy/overridetree.cb
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@ -294,7 +294,7 @@ chip soc/intel/cannonlake
end
end #I2C #4
device pci 1a.0 on end # eMMC
device pci 1c.0 on
device pci 1c.6 on
chip drivers/net
register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW1_07" # GPP_C7
@ -305,8 +305,7 @@ chip soc/intel/cannonlake
register "device_index" = "0"
device pci 00.0 on end
end
end # FSP requires func0 be enabled.
device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1).
end # RTL8111H Ethernet NIC
device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
device pci 1e.3 off end # GSPI #1
end

5
src/mainboard/google/hatch/variants/kaisa/overridetree.cb
View File

@ -294,7 +294,7 @@ chip soc/intel/cannonlake
end
end #I2C #4
device pci 1a.0 on end # eMMC
device pci 1c.0 on
device pci 1c.6 on
chip drivers/net
register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW1_07" # GPP_C7
@ -305,8 +305,7 @@ chip soc/intel/cannonlake
register "device_index" = "0"
device pci 00.0 on end
end
end # FSP requires func0 be enabled.
device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1).
end # RTL8111H Ethernet NIC
device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
device pci 1e.3 off end # GSPI #1
end

5
src/mainboard/google/hatch/variants/puff/overridetree.cb
View File

@ -297,7 +297,7 @@ chip soc/intel/cannonlake
end
end #I2C #4
device pci 1a.0 on end # eMMC
device pci 1c.0 on
device pci 1c.6 on
chip drivers/net
register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW1_07" # GPP_C7
@ -308,8 +308,7 @@ chip soc/intel/cannonlake
register "device_index" = "0"
device pci 00.0 on end
end
end # FSP requires func0 be enabled.
device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1).
end # RTL8111H Ethernet NIC
device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
device pci 1e.3 off end # GSPI #1
end

6
src/mainboard/google/sarien/variants/arcada/devicetree.cb
View File

@ -373,10 +373,10 @@ chip soc/intel/cannonlake
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on
device pci 1d.0 off end # PCI Express Port 9
device pci 1d.1 on
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
end # PCI Express Port 9
device pci 1d.1 on end # PCI Express Port 10
end # PCI Express Port 10
device pci 1d.2 on end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on

2
src/mainboard/system76/lemp9/devicetree.cb
View File

@ -207,7 +207,7 @@ chip soc/intel/cannonlake
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 off end # eMMC
device pci 1c.0 on end # PCI Express Port 1
device pci 1c.0 off end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4

20
src/soc/intel/cannonlake/chip.c
View File

@ -7,6 +7,7 @@
#include <intelblocks/acpi.h>
#include <intelblocks/cfg.h>
#include <intelblocks/itss.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/xdci.h>
#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
@ -16,6 +17,19 @@
#include "chip.h"
static const struct pcie_rp_group pch_lp_rp_groups[] = {
{ .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
{ .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 },
{ 0 }
};
static const struct pcie_rp_group pch_h_rp_groups[] = {
{ .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
{ .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 },
{ .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 },
{ 0 }
};
#if CONFIG(HAVE_ACPI_TABLES)
const char *soc_acpi_name(const struct device *dev)
{
@ -166,6 +180,12 @@ void soc_init_pre_device(void *chip_info)
cnl_configure_pads(NULL, 0);
soc_gpio_pm_configuration();
/* swap enabled PCI ports in device tree if needed */
if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H))
pcie_rp_update_devicetree(pch_h_rp_groups);
else
pcie_rp_update_devicetree(pch_lp_rp_groups);
}
static struct device_operations pci_domain_ops = {