soc/intel/common: Include Icelake device IDs

Add Icelake specific CPU, System Agent, PCH, IGD device IDs.

Change-Id: I2c398957ffbc9bb0e5b363740d99433075ca66a3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/include/device/pci_ids.h

@@ -2692,6 +2692,13 @@
 #define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC	0x9d83
 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370	0xa306
 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370	0xa30c
+#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC	0x3480
+#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0	0x3481
+#define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC	0x3482
+#define PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC		0x3483
+#define PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC		0x3484
+#define PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC	0x3487
+#define PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC	0x3486
 
 /* Intel PCIE device ids  */
 #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1		0x9d10
@@ -2769,6 +2776,22 @@
 #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14		0x9db5
 #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15		0x9db6
 #define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16		0x9db7
+#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP1		0x34b8
+#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP2		0x34b9
+#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP3		0x34ba
+#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP4		0x34bb
+#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP5		0x34bc
+#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP6		0x34bd
+#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP7		0x34be
+#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP8		0x34bf
+#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP9		0x34b0
+#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP10		0x34b1
+#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP11		0x34b2
+#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP12		0x34b3
+#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP13		0x34b4
+#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP14		0x34b5
+#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP15		0x34b6
+#define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP16		0x34b7
 
 #define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP1		0xa338
 #define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP2		0xa339
@@ -2806,6 +2829,7 @@
 #define PCI_DEVICE_ID_INTEL_CNL_COMPAT_SATA	0x282a
 #define PCI_DEVICE_ID_INTEL_CNP_H_SATA		0xa352
 #define PCI_DEVICE_ID_INTEL_CNP_LP_SATA		0x9dd3
+#define PCI_DEVICE_ID_INTEL_ICP_U_SATA		0x34d3
 
 /* Intel PMC device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC		0x9d21
@@ -2815,6 +2839,7 @@
 #define PCI_DEVICE_ID_INTEL_GLK_PMC		0x3194
 #define PCI_DEVICE_ID_INTEL_CNL_PMC		0x9da1
 #define PCI_DEVICE_ID_INTEL_CNP_H_PMC		0xa321
+#define PCI_DEVICE_ID_INTEL_ICP_PMC		0x34a1
 
 /* Intel I2C device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_I2C0		0x9d60
@@ -2853,6 +2878,12 @@
 #define PCI_DEVICE_ID_INTEL_CNP_H_I2C1		0xa369
 #define PCI_DEVICE_ID_INTEL_CNP_H_I2C2		0xa36a
 #define PCI_DEVICE_ID_INTEL_CNP_H_I2C3		0xa36b
+#define PCI_DEVICE_ID_INTEL_ICP_I2C0		0x34e8
+#define PCI_DEVICE_ID_INTEL_ICP_I2C1		0x34e9
+#define PCI_DEVICE_ID_INTEL_ICP_I2C2		0x34ea
+#define PCI_DEVICE_ID_INTEL_ICP_I2C3		0x34eb
+#define PCI_DEVICE_ID_INTEL_ICP_I2C4		0x34c5
+#define PCI_DEVICE_ID_INTEL_ICP_I2C5		0x34c6
 
 /* Intel UART device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_UART0		0x9d27
@@ -2878,6 +2909,9 @@
 #define PCI_DEVICE_ID_INTEL_CNP_H_UART0		0xa328
 #define PCI_DEVICE_ID_INTEL_CNP_H_UART1		0xa329
 #define PCI_DEVICE_ID_INTEL_CNP_H_UART2		0xa347
+#define PCI_DEVICE_ID_INTEL_ICP_UART0		0x34a8
+#define PCI_DEVICE_ID_INTEL_ICP_UART1		0x34a9
+#define PCI_DEVICE_ID_INTEL_ICP_UART2		0x34c7
 
 /* Intel SPI device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_SPI1		0x9d24
@@ -2894,6 +2928,10 @@
 #define PCI_DEVICE_ID_INTEL_CNL_SPI1		0x9dab
 #define PCI_DEVICE_ID_INTEL_CNL_SPI2		0x9dfb
 #define PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI	0x9da4
+#define PCI_DEVICE_ID_INTEL_ICP_SPI0		0x34aa
+#define PCI_DEVICE_ID_INTEL_ICP_SPI1		0x34ab
+#define PCI_DEVICE_ID_INTEL_ICP_SPI2		0x34fb
+#define PCI_DEVICE_ID_INTEL_ICP_HWSEQ_SPI	0x34a4
 
 /* Intel IGD device Ids */
 #define PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM		0x1906
@@ -2925,6 +2963,22 @@
 #define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT			0x3EA5
 #define PCI_DEVICE_ID_INTEL_CFL_H_GT2			0x3e9b
 #define PCI_DEVICE_ID_INTEL_CFL_S_GT2			0x3e92
+#define PCI_DEVICE_ID_INTEL_ICL_GT0_ULT		0x8A70
+#define PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT		0x8A71
+#define PCI_DEVICE_ID_INTEL_ICL_GT1_ULT		0x8A40
+#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_0		0x8A50
+#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_1		0x8A5D
+#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_1		0x8A5B
+#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_2		0x8A5C
+#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_2		0x8A5A
+#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_3		0x8A51
+#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_3		0x8A52
+#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_4		0x8A53
+#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_4		0x8A54
+#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_5		0x8A55
+#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_5		0x8A56
+#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_6		0x8A57
+#define PCI_DEVICE_ID_INTEL_ICL_GT3_ULT		0x8A62
 
 /* Intel Northbridge Ids */
 #define PCI_DEVICE_ID_INTEL_APL_NB	0x5af0
@@ -2947,6 +3001,10 @@
 #define PCI_DEVICE_ID_INTEL_CFL_ID_U	0x3ED0
 #define PCI_DEVICE_ID_INTEL_CFL_ID_H	0x3ec4
 #define PCI_DEVICE_ID_INTEL_CFL_ID_S	0x3ec2
+#define PCI_DEVICE_ID_INTEL_ICL_ID_U	0x8A12
+#define PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2	0x8A02
+#define PCI_DEVICE_ID_INTEL_ICL_ID_Y	0x8A10
+#define PCI_DEVICE_ID_INTEL_ICL_ID_Y_2	0x8A00
 
 /* Intel SMBUS device Ids */
 #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS		0x9d23
@@ -2954,6 +3012,7 @@
 #define PCI_DEVICE_ID_INTEL_KBP_H_SMBUS			0xa1a3
 #define PCI_DEVICE_ID_INTEL_CNL_SMBUS			0x9da3
 #define PCI_DEVICE_ID_INTEL_CNP_H_SMBUS			0xa323
+#define PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS		0x34a3
 
 /* Intel XHCI device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_XHCI		0x5aa8
@@ -2963,18 +3022,21 @@
 #define PCI_DEVICE_ID_INTEL_KBP_H_XHCI		0xa2af
 #define PCI_DEVICE_ID_INTEL_CNL_LP_XHCI		0x9ded
 #define PCI_DEVICE_ID_INTEL_CNP_H_XHCI		0xa36d
+#define PCI_DEVICE_ID_INTEL_ICP_LP_XHCI		0x34ed
 
 /* Intel P2SB device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_P2SB		0x5a92
 #define PCI_DEVICE_ID_INTEL_GLK_P2SB		0x3192
 #define PCI_DEVICE_ID_INTEL_CNL_P2SB		0x9da0
 #define PCI_DEVICE_ID_INTEL_CNP_H_P2SB		0xa320
+#define PCI_DEVICE_ID_INTEL_ICL_P2SB		0x34a0
 
 /* Intel SRAM device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_SRAM		0x5aec
 #define PCI_DEVICE_ID_INTEL_GLK_SRAM		0x31ec
 #define PCI_DEVICE_ID_INTEL_CNL_SRAM		0x9def
 #define PCI_DEVICE_ID_INTEL_CNP_H_SRAM		0xa36f
+#define PCI_DEVICE_ID_INTEL_ICL_SRAM		0x34ef
 
 /* Intel AUDIO device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_AUDIO		0x5a98
@@ -2983,6 +3045,7 @@
 #define PCI_DEVICE_ID_INTEL_SKL_AUDIO		0x9d70
 #define PCI_DEVICE_ID_INTEL_KBL_AUDIO		0x9d71
 #define PCI_DEVICE_ID_INTEL_CNP_H_AUDIO		0xa348
+#define PCI_DEVICE_ID_INTEL_ICL_AUDIO		0x34c8
 
 /* Intel HECI/ME device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_CSE0		0x5a9a
@@ -2990,6 +3053,7 @@
 #define PCI_DEVICE_ID_INTEL_CNL_CSE0		0x9de0
 #define PCI_DEVICE_ID_INTEL_SKL_CSE0		0x9d3a
 #define PCI_DEVICE_ID_INTEL_CNP_H_CSE0		0xa360
+#define PCI_DEVICE_ID_INTEL_ICL_CSE0		0x34e0
 
 /* Intel XDCI device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_XDCI		0x5aaa
@@ -2997,6 +3061,7 @@
 #define PCI_DEVICE_ID_INTEL_SPT_LP_XDCI		0x9d30
 #define PCI_DEVICE_ID_INTEL_CNL_LP_XDCI		0x9dee
 #define PCI_DEVICE_ID_INTEL_CNP_H_XDCI		0xa36e
+#define PCI_DEVICE_ID_INTEL_ICP_LP_XDCI		0x34ee
 
 /* Intel SD device Ids */
 #define PCI_DEVICE_ID_INTEL_APL_SD		0x5aca
@@ -3004,6 +3069,7 @@
 #define PCI_DEVICE_ID_INTEL_SKL_SD		0x9d2d
 #define PCI_DEVICE_ID_INTEL_CNL_SD		0x9df5
 #define PCI_DEVICE_ID_INTEL_CNP_H_SD		0xa375
+#define PCI_DEVICE_ID_INTEL_ICL_SD		0x34f8
 
 /* Intel EMMC device Ids */
 #define PCI_DEVICE_ID_INTEL_SKL_EMMC		0x9d2b

src/soc/intel/common/block/cpu/mp_init.c

@@ -73,6 +73,8 @@ static const struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 },
 	{ X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 },
 	{ X86_VENDOR_INTEL, CPUID_COFFEELAKE_D0 },
+	{ X86_VENDOR_INTEL, CPUID_ICELAKE_A0 },
+	{ X86_VENDOR_INTEL, CPUID_ICELAKE_B0 },
 	{ 0, 0 },
 };
 

src/soc/intel/common/block/cse/cse.c

@@ -519,6 +519,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNL_CSE0,
 	PCI_DEVICE_ID_INTEL_SKL_CSE0,
 	PCI_DEVICE_ID_INTEL_CNP_H_CSE0,
+	PCI_DEVICE_ID_INTEL_ICL_CSE0,
 	0,
 };
 

src/soc/intel/common/block/dsp/dsp.c

@@ -32,6 +32,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_GLK_AUDIO,
 	PCI_DEVICE_ID_INTEL_SKL_AUDIO,
 	PCI_DEVICE_ID_INTEL_CNP_H_AUDIO,
+	PCI_DEVICE_ID_INTEL_ICL_AUDIO,
 	0,
 };
 

src/soc/intel/common/block/graphics/graphics.c

@@ -134,6 +134,22 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM,
 	PCI_DEVICE_ID_INTEL_CFL_H_GT2,
 	PCI_DEVICE_ID_INTEL_CFL_S_GT2,
+	PCI_DEVICE_ID_INTEL_ICL_GT0_ULT,
+	PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT,
+	PCI_DEVICE_ID_INTEL_ICL_GT1_ULT,
+	PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_0,
+	PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_1,
+	PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_1,
+	PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_2,
+	PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_2,
+	PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_3,
+	PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_3,
+	PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_4,
+	PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_4,
+	PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_5,
+	PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_5,
+	PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_6,
+	PCI_DEVICE_ID_INTEL_ICL_GT3_ULT,
 	0,
 };
 

src/soc/intel/common/block/hda/hda.c

@@ -76,6 +76,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_KBL_AUDIO,
 	PCI_DEVICE_ID_INTEL_CNL_AUDIO,
 	PCI_DEVICE_ID_INTEL_CNP_H_AUDIO,
+	PCI_DEVICE_ID_INTEL_ICL_AUDIO,
 	0
 };
 

src/soc/intel/common/block/i2c/i2c.c

@@ -217,6 +217,12 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNP_H_I2C1,
 	PCI_DEVICE_ID_INTEL_CNP_H_I2C2,
 	PCI_DEVICE_ID_INTEL_CNP_H_I2C3,
+	PCI_DEVICE_ID_INTEL_ICP_I2C0,
+	PCI_DEVICE_ID_INTEL_ICP_I2C1,
+	PCI_DEVICE_ID_INTEL_ICP_I2C2,
+	PCI_DEVICE_ID_INTEL_ICP_I2C3,
+	PCI_DEVICE_ID_INTEL_ICP_I2C4,
+	PCI_DEVICE_ID_INTEL_ICP_I2C5,
 	0,
 };
 

src/soc/intel/common/block/include/intelblocks/mp_init.h

@@ -41,6 +41,8 @@
 #define CPUID_COFFEELAKE_D0	0x806ea
 #define CPUID_COFFEELAKE_U0	0x906ea
 
+#define CPUID_ICELAKE_A0	0x706e0
+#define CPUID_ICELAKE_B0	0x706e1
 /*
  * MP Init callback function to Find CPU Topology. This function is common
  * among all SOCs and thus its in Common CPU block.

src/soc/intel/common/block/lpc/lpc.c

@@ -146,6 +146,13 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC,
 	PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370,
 	PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370,
+	PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC,
+	PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC,
+	PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC,
+	PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC,
+	PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0,
+	PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC,
+	PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC,
 	0
 };
 

src/soc/intel/common/block/p2sb/p2sb.c

@@ -167,6 +167,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_GLK_P2SB,
 	PCI_DEVICE_ID_INTEL_CNL_P2SB,
 	PCI_DEVICE_ID_INTEL_CNP_H_P2SB,
+	PCI_DEVICE_ID_INTEL_ICL_P2SB,
 	0,
 };
 

src/soc/intel/common/block/pcie/pcie.c

@@ -190,6 +190,22 @@ static const unsigned short pcie_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP22,
 	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP23,
 	PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP24,
+	PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP1,
+	PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP2,
+	PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP3,
+	PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP4,
+	PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP5,
+	PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP6,
+	PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP7,
+	PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP8,
+	PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP9,
+	PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP10,
+	PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP11,
+	PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP12,
+	PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP13,
+	PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP14,
+	PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP15,
+	PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP16,
 	0
 };
 

src/soc/intel/common/block/pmc/pmc.c

@@ -127,6 +127,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_APL_PMC,
 	PCI_DEVICE_ID_INTEL_GLK_PMC,
 	PCI_DEVICE_ID_INTEL_CNP_H_PMC,
+	PCI_DEVICE_ID_INTEL_ICP_PMC,
 	0
 };
 

src/soc/intel/common/block/sata/sata.c

@@ -78,6 +78,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNL_COMPAT_SATA,
 	PCI_DEVICE_ID_INTEL_CNP_H_SATA,
 	PCI_DEVICE_ID_INTEL_CNP_LP_SATA,
+	PCI_DEVICE_ID_INTEL_ICP_U_SATA,
 	0
 };
 

src/soc/intel/common/block/scs/sd.c

@@ -71,6 +71,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_GLK_SD,
 	PCI_DEVICE_ID_INTEL_SKL_SD,
 	PCI_DEVICE_ID_INTEL_CNP_H_SD,
+	PCI_DEVICE_ID_INTEL_ICL_SD,
 	0
 };
 

src/soc/intel/common/block/smbus/smbus.c

@@ -92,6 +92,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS,
 	PCI_DEVICE_ID_INTEL_SPT_H_SMBUS,
 	PCI_DEVICE_ID_INTEL_KBP_H_SMBUS,
+	PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS,
 	0
 };
 

src/soc/intel/common/block/spi/spi.c

@@ -67,6 +67,10 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNL_SPI1,
 	PCI_DEVICE_ID_INTEL_CNL_SPI2,
 	PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI,
+	PCI_DEVICE_ID_INTEL_ICP_SPI0,
+	PCI_DEVICE_ID_INTEL_ICP_SPI1,
+	PCI_DEVICE_ID_INTEL_ICP_SPI2,
+	PCI_DEVICE_ID_INTEL_ICP_HWSEQ_SPI,
 	0
 };
 

src/soc/intel/common/block/sram/sram.c

@@ -49,6 +49,7 @@ static const struct device_operations device_ops = {
 static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_APL_SRAM,
 	PCI_DEVICE_ID_INTEL_GLK_SRAM,
+	PCI_DEVICE_ID_INTEL_ICL_SRAM,
 	0,
 };
 

src/soc/intel/common/block/systemagent/systemagent.c

@@ -306,6 +306,10 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DEVICE_ID_INTEL_CFL_ID_U,
 	PCI_DEVICE_ID_INTEL_CFL_ID_H,
 	PCI_DEVICE_ID_INTEL_CFL_ID_S,
+	PCI_DEVICE_ID_INTEL_ICL_ID_U,
+	PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2,
+	PCI_DEVICE_ID_INTEL_ICL_ID_Y,
+	PCI_DEVICE_ID_INTEL_ICL_ID_Y_2,
 	0
 };
 

src/soc/intel/common/block/uart/uart.c

@@ -265,6 +265,9 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNP_H_UART0,
 	PCI_DEVICE_ID_INTEL_CNP_H_UART1,
 	PCI_DEVICE_ID_INTEL_CNP_H_UART2,
+	PCI_DEVICE_ID_INTEL_ICP_UART0,
+	PCI_DEVICE_ID_INTEL_ICP_UART1,
+	PCI_DEVICE_ID_INTEL_ICP_UART2,
 	0,
 };
 

src/soc/intel/common/block/xdci/xdci.c

@@ -42,6 +42,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_GLK_XDCI,
 	PCI_DEVICE_ID_INTEL_SPT_LP_XDCI,
 	PCI_DEVICE_ID_INTEL_CNP_H_XDCI,
+	PCI_DEVICE_ID_INTEL_ICP_LP_XDCI,
 	0
 };
 

src/soc/intel/common/block/xhci/xhci.c

@@ -43,6 +43,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_SPT_H_XHCI,
 	PCI_DEVICE_ID_INTEL_KBP_H_XHCI,
 	PCI_DEVICE_ID_INTEL_CNP_H_XHCI,
+	PCI_DEVICE_ID_INTEL_ICP_LP_XHCI,
 	0
 };
 

src/soc/intel/icelake/bootblock/report_platform.c

@@ -31,55 +31,52 @@ static struct {
 	u32 cpuid;
 	const char *name;
 } cpu_table[] = {
-	{ CPUID_CANNONLAKE_A0, "Cannonlake A0" },
-	{ CPUID_CANNONLAKE_B0, "Cannonlake B0" },
-	{ CPUID_CANNONLAKE_C0, "Cannonlake C0" },
-	{ CPUID_CANNONLAKE_D0, "Cannonlake D0" },
-	{ CPUID_COFFEELAKE_D0, "Coffeelake D0" },
-	{ CPUID_WHISKEYLAKE_W0, "Whiskeylake W0"},
-	{ CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" },
+	{ CPUID_ICELAKE_A0, "Icelake A0" },
+	{ CPUID_ICELAKE_B0, "Icelake B0" },
 };
 
 static struct {
 	u16 mchid;
 	const char *name;
 } mch_table[] = {
-	{ PCI_DEVICE_ID_INTEL_CNL_ID_U, "Cannonlake-U" },
-	{ PCI_DEVICE_ID_INTEL_CNL_ID_Y, "Cannonlake-Y" },
-	{ PCI_DEVICE_ID_INTEL_CFL_ID_U, "Coffeelake U (4+3e)"},
-	{ PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, "Whiskeylake W (4+2)"},
-	{ PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, "Whiskeylake W (2+2)"},
-	{ PCI_DEVICE_ID_INTEL_CFL_ID_H, "Coffeelake-H" },
-	{ PCI_DEVICE_ID_INTEL_CFL_ID_S, "Coffeelake-S" },
+	{ PCI_DEVICE_ID_INTEL_ICL_ID_U, "Icelake-U" },
+	{ PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2, "Icelake-U-2-2" },
+	{ PCI_DEVICE_ID_INTEL_ICL_ID_Y, "Icelake-Y" },
+	{ PCI_DEVICE_ID_INTEL_ICL_ID_Y_2, "Icelake-Y-2" },
 };
 
 static struct {
 	u16 lpcid;
 	const char *name;
 } pch_table[] = {
-	{ PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, "Cannonlake-U Base" },
-	{ PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, "Cannonlake-U Premium" },
-	{ PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" },
-	{ PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, "Cannonlake-H Q370" },
-	{ PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, "Cannonlake-H QM370" },
+	{ PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC, "Icelake-U Base" },
+	{ PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC, "Icelake-Y Base" },
+	{ PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC, "Icelake-U Premium" },
+	{ PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC, "Icelake-U Super" },
+	{ PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0, "Icelake-U Super REV0" },
+	{ PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC, "Icelake-Y Super" },
+	{ PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC, "Icelake-Y Premium" },
 };
 
 static struct {
 	u16 igdid;
 	const char *name;
 } igd_table[] = {
-	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1, "Cannonlake ULX GT2" },
-	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2, "Cannonlake ULX GT1.5" },
-	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3, "Cannonlake ULX GT1" },
-	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_4, "Cannonlake ULX GT0.5" },
-	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_1, "Cannonlake ULT GT2" },
-	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2, "Cannonlake ULT GT1.5" },
-	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3, "Cannonlake ULT GT1" },
-	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" },
-	{ PCI_DEVICE_ID_INTEL_CFL_GT2_ULT, "Coffeelake ULT GT2"},
-	{ PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT1"},
-	{ PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" },
-	{ PCI_DEVICE_ID_INTEL_CFL_S_GT2, "Coffeelake-S GT2" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT0_ULT, "Icelake ULT GT0" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT, "Icelake ULT GT0.5" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT1_ULT, "Icelake U GT1" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_0, "Icelake Y GT2" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_1, "Icelake Y GT2_1" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_1, "Icelake U GT2_1" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_2, "Icelake Y GT2_2" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_2, "Icelake U GT2_2" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_3, "Icelake Y GT2_3" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_3, "Icelake U GT2_3" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_4, "Icelake Y GT2_4" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_4, "Icelake U GT2_4" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_5, "Icelake Y GT2_5" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_5, "Icelake U GT2_5" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT3_ULT, "Icelake U GT3" },
 };
 
 static uint8_t get_dev_revision(pci_devfn_t dev)